06-03-2019 11:52 PM
hii.. Is there any way to create a time bound netlist in vivado. I want a netlist to be generated which is valid only for certain amount of time.
06-04-2019 03:00 AM
I don't know if this is the best method....
Have your sys_clk gated.
Have a counter that will count up with the sys_clk, When the desired time/count value is reached, have a signal going HIGH/LOW that will disable the supply of the sys_clk.
Many of the xilinx evaluation encrypted IP cores have a timeout duration but I don't know how they are doing it. Maybe Xilinx support will throw more light on this.
06-04-2019 03:18 AM - edited 06-04-2019 03:21 AM
hi paul, Thanks for replying..counter soultion is secondary for me.. I thought the same, manipulating the RTL. But I am more interested Is there any way in the tool itself..So that it will create a timebound netlist.
06-04-2019 06:29 AM
I am unaware of any features in Vivado that will automatically add a "timebomb" to a netlist. The counter method mentioned before is what I have seen in the past.
06-05-2019 04:06 AM - edited 06-05-2019 04:48 AM
Have you used the evaluation version of the Xilinx TEMAC core? This evaluation core version (encrypted) has a time-bomb that shuts the core off after ~2hrs of operation.
I don't think anyone from Xilinx will disclose how they are doing it here in this forum.
06-05-2019 05:35 AM
I haven't used the eval version of theTEMAC IP. I have used eval versions of some of the other cores. I don't have specific information about the implementation of the Timebomb, but I believe that it is a counter tied to the clock enable or the reset. When a core is compiled with a valid license, the Timebomb is excluded from the netlist.
06-05-2019 10:22 PM
Thankyou for your time to shed some light in this query. I havn't used the eval version, but I am pretty much sure the source code won't be visible. So to summarize the points.
1. There is no settings in the tool to create a timebomb netlist.
2. If need to create, one needs to implement a counter that will manipulate the clock of the system,
One possiblity which I thought of is to make a counter and the output of which is conditioned with the state of the FSM resulting to reset the system.
06-06-2019 06:02 AM
I would agree with both of your point with one small suggestion. When implementing the counter in your design, do not directly control the actual clock with the counter. You do not want to create a gated clock which will require moving the clock off of the dedicated clock traces and onto the general fabric traces. It can be made to work but could open up all kinds of timing analysis problems. It's equally valid to use the reset and much safer.