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Newbie
5,038 Views
Registered: ‎05-01-2009

unsure on how to implement a given circuit

Can someone please help me understand how to design and implement the given circuit with the given instructions?

Don't give me the code, just explain it in plain English what I need to do to satisfy the requirement.  Thanks...

There are four D Flip-flops on the following diagram: R0, R1, R2, and R3.

You must use
the following hardware structures and use the given data path below.

First, write Verilog programs to implement the following datapath:

1). DFF.v

Help Tip:

always@(posedge clk)

begin

if(clr)

q <= 0;

else if(ce)

q<= d;

end

2). MUX2to1.v 3). MUX4to1.v

4). ALU.v 5). DATAPATH.v

Inside DATAPATH.v, create instances for DFF, MUX2to1, MUX4 to 1, ALU and use

hierarchical design to connect them together.

im working on lab 3 part 1

Given the datapath above, design a finite state machine controller to implement one of

the following functions:

(0). R2 = M0 or [ inv(M1) ]

(1). R2 = M0 + M1 + Cin (2). R2 = M0 + inv(M1) + Cin

(3). R2 = M0 and M1 (4). R2 = M0 nand M1

(5). R2 = M0 or M1 (6). R2 = M0 xor M1

(7). R2 =[ inv(M0) ] and M1 (8). R2 = M0 xnor M1

(9). R2 = M0 nor M1

Load M0, M1 to registers R0 and R1, store the final ALU result in register R2.

Choose one function according to the last digit of your student number.

If the last digit of your student number is 0, implement function (0).

If the last digit of your student number is 1, implement function (1).

If the last digit of your student number is 9, implement function (9).

TOP.v

You need to create one instance of DATAPAH and design one Finite State Machine to control it.

Your finite state machine should generate the following control signals:

clr, W, S, CE, and sel.

If reset signal is equal to logic ‘1’, your finite state machine should be in idle state.

Else

if start signal is equal to logic ‘1’, your finite state machine will start to work.

module top( reset, start, clk, M0, M1, M2, Cin, clr, W, S, CE, R, Y, sel, A, B );

input reset, start, clk, M0, M1, M2, Cin;

output clr;

output [2:0] W, S;

output [3:0] CE, R, Y;

output [1:0] sel;

output A, B;

……..

endmodule

3 Replies
Historian
5,012 Views
Registered: ‎02-25-2008
Sorry, you are failing your course.
----------------------------Yes, I do this for a living.
Xilinx Employee
4,998 Views
Registered: ‎08-13-2007

I would suggest meeting with your professor or teaching assistant for additional help if the instructions above are insufficient.

bt

Voyager
4,891 Views
Registered: ‎08-30-2007

Well, we can't do your homework for you, and it looks like you may not want us to!

I'd suggest you break the overall problem down into a set of smaller tasks to accomplish, then tackle them one by one.

So, write your mux, datapath and alu blocks.  You need to think about what each module will need to do, then write the logic.

A simple approach might be to think "I don't care what's actually  in the low level blocks right now, I'll just focus on creating the

module wrappers and hooking them together." Thus,you'll define the input/outputs for each module and write the Verilog

wrapper for it.

This should hook up the overall design.   If done properly, you can feed the design using these empty wrappers into a

simulator so you can eliminate any/all syntax errors.

After that, start filling in each module with actual code.  Start with the easy ones so you have some success, then tackle

the hard one.

AN ALTERNATE APPROACH....

create each sub module (for example mux2to1) then test it in simulation so you know that buildin block is correct,

then proceed to the next module.  Like the 1st approach, you tackle one small piece of the project at a time.

So my advice - don't get overwhelmed by the "big picture". Break it into small pieces that you can understand, then

put them together.

I hope this helps!

John Providenza