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Visitor geyi1990
Visitor
724 Views
Registered: ‎04-19-2018

vivado 2017.2 error place [30-487]

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[Place 30-487] The packing of instances into a set of slices defined by an internal area constraint could not be obeyed. Please analyze your design to determine if the number of LUTs, FFs, and/or control sets can be reduced.

Number of instances constrained to the area constraint:
Flip flops: 9896 in the design area under consideration, 26400 available in the area constraint (NOTE: each slice can only accomodate 1 unique control set so FFs cannot be packed to fully fill every slice)
Luts: 8624(combined) 11180 (total) in design area under consideration, 13200 available in area constraint
Control sets: 565 in area constraint
The unplaced instances require 3030 slices but only 2602 out of 3300 slices in the area constraint are available, because others may be occupied by placed instances or blocked by exclude placement.


To attempt placement at higher effort levels at the expense of runtime, please use the following tcl command, setting the value of limit to 2000 or more.
set_param place.sliceLegEffortLimit limit

 

I found out that I used BUFR to divide by 2 in the clock structure. This error occurred in the place. When I replace the BUFR I can run impl. I use the A7 platform. I think the A7 platform supports BUFR. Why can't BUFR be used in the design?

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Scholar watari
Scholar
957 Views
Registered: ‎06-16-2013

Re: vivado 2017.2 error place [30-487]

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Hi @geyi1990

 

BUFR is for regional clock. Not global clock.

I guess, in this case, vivado could not route clock path with BUFR cell. Because of the location of BUFR was not fine.

(Maybe there are so many leaf cells in your design.)

 

If you meet your target, I suggest to consider floor plan to gather related modules.

 

Best regards,

 

1 Reply
Scholar watari
Scholar
958 Views
Registered: ‎06-16-2013

Re: vivado 2017.2 error place [30-487]

Jump to solution

Hi @geyi1990

 

BUFR is for regional clock. Not global clock.

I guess, in this case, vivado could not route clock path with BUFR cell. Because of the location of BUFR was not fine.

(Maybe there are so many leaf cells in your design.)

 

If you meet your target, I suggest to consider floor plan to gather related modules.

 

Best regards,