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Explorer
Explorer
329 Views
Registered: ‎10-12-2016

vivado hang at implementation stage

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HI Friends, 
 
Vivado hanged at implementation stage, The following is the part of the log. 
 
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: de18dbfe

Time (s): cpu = 00:12:38 ; elapsed = 00:05:55 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37826 ; free virtual = 305010

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 10af736b8

Time (s): cpu = 00:12:39 ; elapsed = 00:05:56 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37826 ; free virtual = 305010

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1322065c0

Time (s): cpu = 00:13:08 ; elapsed = 00:06:05 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37826 ; free virtual = 305009

Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 120bd5fa7

Time (s): cpu = 00:13:12 ; elapsed = 00:06:08 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37824 ; free virtual = 305008

Phase 3.7 Small Shape Detail Placement
Phase 3.7 Small Shape Detail Placement | Checksum: 1f61613fa

Time (s): cpu = 00:14:44 ; elapsed = 00:07:35 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37826 ; free virtual = 305009

Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 19e1fde1b

Time (s): cpu = 00:14:55 ; elapsed = 00:07:46 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37826 ; free virtual = 305010

Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 17a57fb70

Time (s): cpu = 00:14:59 ; elapsed = 00:07:48 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37826 ; free virtual = 305010

Phase 3.10 Fast Optimization
Phase 3.10 Fast Optimization | Checksum: 162effcf9

Time (s): cpu = 00:16:04 ; elapsed = 00:08:14 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37824 ; free virtual = 305008
Phase 3 Detail Placement | Checksum: 162effcf9

Time (s): cpu = 00:16:07 ; elapsed = 00:08:16 . Memory (MB): peak = 3162.438 ; gain = 7.012 ; free physical = 37824 ; free virtual = 305008

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

 

 

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1 Solution

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Explorer
Explorer
144 Views
Registered: ‎10-12-2016

Re: vivado hang at implementation stage

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HI ,

 

I tried 2017.4 but getting same issue, The problem in my case is tool automatically assining pin locs for some ports because of mismatch of ports in xdc and top file. mainly clock pins are changed in my case. now it is fine.

 

Thank You

S Sampath

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5 Replies
Voyager
Voyager
325 Views
Registered: ‎10-23-2018

Re: vivado hang at implementation stage

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@ssampath

How long did you allow it finish?

What version you running? (2018.3 appears to be much faster than 2018.2 in my testing)

Is you design 'large' (or have large case statements, processes, ...)?

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Explorer
Explorer
311 Views
Registered: ‎10-12-2016

Re: vivado hang at implementation stage

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HI , 

am using 2016.4 and design not that much big. since 5 hrs it is in same state. 

Once i will try with 2018.2 version. 

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Voyager
Voyager
304 Views
Registered: ‎10-23-2018

Re: vivado hang at implementation stage

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@ssampath

Yes, try with a newer version.

One other reason I have seen reported, was when the design was recursive (and then ran out of memory and when in to swap)

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Moderator
Moderator
157 Views
Registered: ‎01-16-2013

Re: vivado hang at implementation stage

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@ssampath

 

Did you try in vivado 2018.x as suggested above? Also, try to remove any wild cards in XDC or clean up the timing constraints to make it simple

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Explorer
Explorer
145 Views
Registered: ‎10-12-2016

Re: vivado hang at implementation stage

Jump to solution

HI ,

 

I tried 2017.4 but getting same issue, The problem in my case is tool automatically assining pin locs for some ports because of mismatch of ports in xdc and top file. mainly clock pins are changed in my case. now it is fine.

 

Thank You

S Sampath

0 Kudos