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phil_morrell
Visitor
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7,471 Views
Registered: ‎04-27-2015

vivado message question

After upgrading to 2015.4 I am seeing a new output message during placement.

 

Phase 2 Global Placement
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]

 

Any idea what it means?

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3 Replies
syedz
Moderator
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7,437 Views
Registered: ‎01-16-2013

@phil_morrell,

 

Did you upgrade all the IP after migrating to 2015.4? Run the following TCL command in Vivado TCL console and share the output:

report_ip_status

 

If possible, Can you please share the post opt dcp chekcpoint file which will be located under "<project>.runs/impl_1/**opt.dcp"

 

--Syed

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phil_morrell
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Registered: ‎04-27-2015

Yes, the IP's have been upgraded. Would have been nice to know that the old style of IP folders can not be in the same directory as the new xcix file that is used to encapsulate the IP now. Once I deleted the old style folders things worked much better.

 

I will need an ftp address to send the opt dcp.

 

Here is the report ip...

 

report_ip_status
Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
| Date         : Fri Dec 11 08:51:14 2015
| Host         : pmorrell-w7822 running 64-bit Service Pack 1  (build 7601)
| Command      : report_ip_status
------------------------------------------------------------------------------------

IP Status Summary

1. Project IP Status
--------------------
Your project uses 8 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions.

More information on the Xilinx versioning policy is available at www.xilinx.com.

Project IP Instances
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| Instance Name            | Status     | Recommendation      | Change    | IP Name            | IP      | New Version  | New        | Original Part        |
|                          |            |                     | Log       |                    | Version |              | License    |                      |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| MMS_V4_mig               | Up-to-date | No changes required |  *(1)     | Memory Interface   | 2.4     | 2.4 (Rev. 1) | Included   | xc7a200tfbg484-2     |
|                          |            |                     |           | Generator (MIG 7   | (Rev.   |              |            |                      |
|                          |            |                     |           | Series)            | 1)      |              |            |                      |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| RW12kx32_RO12kx32        | Up-to-date | No changes required |  *(2)     | Block Memory       | 8.3     | 8.3 (Rev. 1) | Included   | xc7a200tfbg484-2     |
|                          |            |                     |           | Generator          | (Rev.   |              |            |                      |
|                          |            |                     |           |                    | 1)      |              |            |                      |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| SINE_DPROM_4Kx32         | Up-to-date | No changes required |  *(3)     | Block Memory       | 8.3     | 8.3 (Rev. 1) | Included   | xc7a200tfbg484-2     |
|                          |            |                     |           | Generator          | (Rev.   |              |            |                      |
|                          |            |                     |           |                    | 1)      |              |            |                      |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| clk_gen                  | Up-to-date | No changes required |  *(4)     | Clocking Wizard    | 5.2     | 5.2 (Rev. 1) | Included   | xc7a200tfbg484-2     |
|                          |            |                     |           |                    | (Rev.   |              |            |                      |
|                          |            |                     |           |                    | 1)      |              |            |                      |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| dds_sync_clk_wiz         | Up-to-date | No changes required |  *(5)     | Clocking Wizard    | 5.2     | 5.2 (Rev. 1) | Included   | xc7a200tfbg484-2     |
|                          |            |                     |           |                    | (Rev.   |              |            |                      |
|                          |            |                     |           |                    | 1)      |              |            |                      |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| fir_5_15_80db            | Up-to-date | No changes required |  *(6)     | FIR Compiler       | 7.2     | 7.2 (Rev. 5) | Included   | xc7a200tfbg484-2     |
|                          |            |                     |           |                    | (Rev.   |              |            |                      |
|                          |            |                     |           |                    | 5)      |              |            |                      |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| signedDiv32_32_remainder | Up-to-date | No changes required |  *(7)     | Divider Generator  | 5.1     | 5.1 (Rev. 9) | Included   | xc7a200tfbg484-2     |
|                          |            |                     |           |                    | (Rev.   |              |            |                      |
|                          |            |                     |           |                    | 9)      |              |            |                      |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
| xadc_wiz_0               | Up-to-date | No changes required | *(8)      | XADC Wizard        | 3.2     | 3.2          | Included   | xc7a200tfbg484-2     |
+--------------------------+------------+---------------------+-----------+--------------------+---------+--------------+------------+----------------------+
*(1) c:/Xilinx/Vivado/2015.4/data/ip/xilinx/mig_7series_v2_4/doc/mig_7series_v2_4_changelog.txt
*(2) c:/Xilinx/Vivado/2015.4/data/ip/xilinx/blk_mem_gen_v8_3/doc/blk_mem_gen_v8_3_changelog.txt
*(3) c:/Xilinx/Vivado/2015.4/data/ip/xilinx/blk_mem_gen_v8_3/doc/blk_mem_gen_v8_3_changelog.txt
*(4) c:/Xilinx/Vivado/2015.4/data/ip/xilinx/clk_wiz_v5_2/doc/clk_wiz_v5_2_changelog.txt
*(5) c:/Xilinx/Vivado/2015.4/data/ip/xilinx/clk_wiz_v5_2/doc/clk_wiz_v5_2_changelog.txt
*(6) c:/Xilinx/Vivado/2015.4/data/ip/xilinx/fir_compiler_v7_2/doc/fir_compiler_v7_2_changelog.txt
*(7) c:/Xilinx/Vivado/2015.4/data/ip/xilinx/div_gen_v5_1/doc/div_gen_v5_1_changelog.txt
*(8) c:/Xilinx/Vivado/2015.4/data/ip/xilinx/xadc_wiz_v3_2/doc/xadc_wiz_v3_2_changelog.txt

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anupkini
Participant
Participant
4,596 Views
Registered: ‎05-16-2012

Hi,

 

I am also getting a similar message in Vivado 2015.4.

Any specific reason for this message ?

 

I have a block design with MIG and AXI Interconnect, the block design was created fresh in 2015.4.

 

Phase 2 Global Placement
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]
QPProb[0] Falling back to DIAG preconditioner for dim[0]
QPProb[0] Falling back to DIAG preconditioner for dim[1]
Phase 2 Global Placement | Checksum: 19689d0ed

 

 

Thanks,

Anup.

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