UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie clancy
Newbie
5,277 Views
Registered: ‎03-14-2014

vivado support for black box within black box

I have a system that I am trying to implemement that includes a black box module (instance u_tm_.... below) and that black box module also includes another black box module(instance ucolumn... below). I added edifs for both black box modules to my vivado project but the lowest level black box is being reported as missing.

 

i.e.

 

    • [Opt 31-30] Blackbox umw_logic/u_tm_...../umemory_controller_top/ucolumn_array_0 (column_array) is driving pin I2 of primitive cell umw_logic/u_tm_..../umemory_controller_top/user_ord_qout[0]_i_2. This blackbox cannot be found in the existing library.

 

Can anyone identify the proper procedure for making this work?

 

Best regards,

Bob

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
5,271 Views
Registered: ‎09-20-2012

Re: vivado support for black box within black box

Hi Bob,

 

Looks like you have added the EDIF files for the blackboxes to the project and still seeing the error.

 

Try changing to manual compile order within the Vivado GUI and select the order the EDIF files are included in the project. See if this helps.

 

Thanks,

Deepika.

Thanks,
Deepika.
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (the star on the left)
0 Kudos