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sam025023
Explorer
Explorer
3,848 Views
Registered: ‎11-11-2013

vivado zynq implementation error: [Drc 23-20] Rule violation

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Hi There,

I am using vivado 2016.2 in Win10 for zynq7020.

 

My clocking scheme is zynq PS FCLK_CLK0-- > input of clocking wizard IP input (Primitive PLL).

 

Synthesis is ok, but it failed in implementation.

 

[Drc 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity.- ***** with COMPENSATION mode ZHOLD must be driven by a clock capable IO.

 

 

Please help!

 

 

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balkris
Xilinx Employee
Xilinx Employee
6,616 Views
Registered: ‎08-01-2008
Can you try running the design in latest Vivado tool

The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.

Refer to page-85 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
Thanks and Regards
Balkrishan
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balkris
Xilinx Employee
Xilinx Employee
6,617 Views
Registered: ‎08-01-2008
Can you try running the design in latest Vivado tool

The ISE or Vivado design tools automatically select the appropriate compensation based on circuit topology. However in your case it looks like it chose this incorrectly as ZHOLD. When the clock input of PLL is coming from BUFG then the compensation factor should be BUF_IN.

Refer to page-85 of http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

View solution in original post

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