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Observer mahadevanna
Observer
9,380 Views
Registered: ‎12-28-2010

what is ngo build error and how it can be overcome

i had a model i had complied it , and it was working fine . when i did save as and complied that saved file it was showing ngo error and when i again complied the original file again it was ngo error . i am totally confused whats happening once it will compile properly and next time it will show error so what is ngo build error and how it can be overcome.

 

waiting for the reply

mahadev

0 Kudos
8 Replies
Xilinx Employee
Xilinx Employee
9,375 Views
Registered: ‎08-23-2008

Re: what is ngo build error and how it can be overcome

What is the ngo error message? 

 

When you are trying to compile the saved file, please cleanup the project files by going to Project --> Cleanup Project Files... and then run the design. See if this makes any difference.

 

Thanks

 

0 Kudos
Observer mahadevanna
Observer
9,374 Views
Registered: ‎12-28-2010

Re: what is ngo build error and how it can be overcome

error is 

ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow
execution...
0 Kudos
Xilinx Employee
Xilinx Employee
9,372 Views
Registered: ‎08-23-2008

Re: what is ngo build error and how it can be overcome

can you please try this:

 

In the XPS project directory, open the etc/fast_runtime.opt file and comment out the following line: 

 

-bm .bmm # Block RAM memory map file

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Observer mahadevanna
Observer
9,367 Views
Registered: ‎12-28-2010

Re: what is ngo build error and how it can be overcome

i did not get u ... how to clean up project files .. just by deleting the files?

0 Kudos
Observer mahadevanna
Observer
9,366 Views
Registered: ‎12-28-2010

Re: what is ngo build error and how it can be overcome

complete error is 

 

 

 

Release 10.1.03 Xflow K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
xflow.exe -p xc2s200e-6pq208 -implement balanced_jtag.opt -config
bitgen_jtag.opt jtagcosim_top  
.... Copying flowfile c:/xilinx/10.1/ise/xilinx/data/fpga.flw into working
directory C:\Documents and Settings\Administrador\Desktop\hwcosim1\xflow 
Using Flow File: C:\Documents and
Settings\Administrador\Desktop\hwcosim1\xflow/fpga.flw 
Using Option File(s): 
 C:\Documents and
Settings\Administrador\Desktop\hwcosim1\xflow/balanced_jtag.opt 
 C:\Documents and Settings\Administrador\Desktop\hwcosim1\xflow/bitgen_jtag.opt 
Creating Script File ... 
#----------------------------------------------#
# Starting program ngdbuild
# ngdbuild -p xc2s200e-6pq208 -nt timestamp -intstyle xflow "C:\Documents and
Settings\Administrador\Desktop\hwcosim1\xflow/jtagcosim_top.ngc"
jtagcosim_top.ngd 
#----------------------------------------------#
Command Line: ngdbuild -p xc2s200e-6pq208 -nt timestamp -intstyle xflow
C:\Documents and Settings\Administrador\Desktop\hwcosim1\xflow/jtagcosim_top.ngc
jtagcosim_top.ngd
Reading NGO file "C:/Documents and
Settings/Administrador/Desktop/hwcosim1/xflow/jtagcosim_top.ngc" ...
Loading design module "C:/Documents and
Settings/Administrador/Desktop/hwcosim1/xflow/jtagcosim_iface_virtex.ngc"...
ERROR:NgdBuild:76 - File "C:/Documents and
   Settings/Administrador/Desktop/hwcosim1/xflow/jtagcosim_iface_virtex.ngc"
   cannot be merged into block "jtag_iface" (TYPE="jtagcosim_iface_virtex")
   because one or more pins on the block, including pin "re", were not found in
   the file.  Please make sure that all pins on the instantiated component match
   pins in the lower-level design block (irrespective of case).  If there are
   bussed pins on this block, make sure that the upper-level and lower-level
   netlists use the same bus-naming convention.
Loading design module "C:/Documents and
Settings/Administrador/Desktop/hwcosim1/xflow/ifir_final2_cw.ngc"...
Loading design module "C:/Documents and
Settings/Administrador/Desktop/hwcosim1/xflow/xlpersistentdff.ngc"...
Executing edif2ngd -noa
"distributed_arithmetic_fir_filter_spartan2_9_0_9e81e7a9fd77e066.edn"
"distributed_arithmetic_fir_filter_spartan2_9_0_9e81e7a9fd77e066.ngo"
Release 10.1.03 - edif2ngd K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 10.1.03 edif2ngd K.39 (nt)
INFO:NgdBuild - Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
Writing module to
"distributed_arithmetic_fir_filter_spartan2_9_0_9e81e7a9fd77e066.ngo"...
Loading design module "C:\Documents and
Settings\Administrador\Desktop\hwcosim1\xflow\distributed_arithmetic_fir_filter_
spartan2_9_0_9e81e7a9fd77e066.ngo"...
Executing edif2ngd -noa
"distributed_arithmetic_fir_filter_spartan2_9_0_62ef61469fa8be5d.edn"
"distributed_arithmetic_fir_filter_spartan2_9_0_62ef61469fa8be5d.ngo"
Release 10.1.03 - edif2ngd K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 10.1.03 edif2ngd K.39 (nt)
INFO:NgdBuild - Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
Writing module to
"distributed_arithmetic_fir_filter_spartan2_9_0_62ef61469fa8be5d.ngo"...
Loading design module "C:\Documents and
Settings\Administrador\Desktop\hwcosim1\xflow\distributed_arithmetic_fir_filter_
spartan2_9_0_62ef61469fa8be5d.ngo"...
Gathering constraint information from source properties...
Done.
Applying constraints in "jtagcosim_top.ucf" to the design...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking Partitions ...
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'jtag_iface' with type
   'jtagcosim_iface_virtex' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, or the misspelling of a type name.
   Symbol 'jtagcosim_iface_virtex' is not supported in target 'spartan2e'.
WARNING:NgdBuild:443 - SFF primitive
   'sysgen_hwcosim_iface/sysgen_dut/default_clock_driver_x0/xlclockdriver_1/clr_
   reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp'
   has unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/vali
   d_pipe/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp'
   has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[0].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[1].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[2].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[3].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[4].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[5].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[6].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[7].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[8].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[9].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[10].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[11].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[12].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la
   tency_test.reg/partial_one.last_srl17e/reg_array[13].fde_used.u2' has
   unconnected output pin
WARNING:NgdBuild:443 - SFF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/va
   lid_pipe/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_com
   p' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core
   _instance/BU10517' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core
   _instance/BU10523' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core
   _instance/BU10529' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core
   _instance/BU10535' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core
   _instance/BU10540' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/co
   re_instance/BU3081' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/co
   re_instance/BU3087' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/co
   re_instance/BU3093' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/co
   re_instance/BU3098' has unconnected output pin
Partition Implementation Status
-------------------------------
  No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
  Number of errors:     1
  Number of warnings:  22
One or more errors were found during NGDBUILD.  No NGD file will be written.
Writing NGDBUILD log file "jtagcosim_top.bld"...
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
    

Release 10.1.03 Xflow K.39 (nt)Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.xflow.exe -p xc2s200e-6pq208 -implement balanced_jtag.opt -configbitgen_jtag.opt jtagcosim_top  .... Copying flowfile c:/xilinx/10.1/ise/xilinx/data/fpga.flw into workingdirectory C:\Documents and Settings\Administrador\Desktop\hwcosim1\xflow 
Using Flow File: C:\Documents andSettings\Administrador\Desktop\hwcosim1\xflow/fpga.flw Using Option File(s):  C:\Documents andSettings\Administrador\Desktop\hwcosim1\xflow/balanced_jtag.opt  C:\Documents and Settings\Administrador\Desktop\hwcosim1\xflow/bitgen_jtag.opt 
Creating Script File ... 
#----------------------------------------------## Starting program ngdbuild# ngdbuild -p xc2s200e-6pq208 -nt timestamp -intstyle xflow "C:\Documents andSettings\Administrador\Desktop\hwcosim1\xflow/jtagcosim_top.ngc"jtagcosim_top.ngd #----------------------------------------------#
Command Line: ngdbuild -p xc2s200e-6pq208 -nt timestamp -intstyle xflowC:\Documents and Settings\Administrador\Desktop\hwcosim1\xflow/jtagcosim_top.ngcjtagcosim_top.ngd
Reading NGO file "C:/Documents andSettings/Administrador/Desktop/hwcosim1/xflow/jtagcosim_top.ngc" ...Loading design module "C:/Documents andSettings/Administrador/Desktop/hwcosim1/xflow/jtagcosim_iface_virtex.ngc"...ERROR:NgdBuild:76 - File "C:/Documents and   Settings/Administrador/Desktop/hwcosim1/xflow/jtagcosim_iface_virtex.ngc"   cannot be merged into block "jtag_iface" (TYPE="jtagcosim_iface_virtex")   because one or more pins on the block, including pin "re", were not found in   the file.  Please make sure that all pins on the instantiated component match   pins in the lower-level design block (irrespective of case).  If there are   bussed pins on this block, make sure that the upper-level and lower-level   netlists use the same bus-naming convention.Loading design module "C:/Documents andSettings/Administrador/Desktop/hwcosim1/xflow/ifir_final2_cw.ngc"...Loading design module "C:/Documents andSettings/Administrador/Desktop/hwcosim1/xflow/xlpersistentdff.ngc"...Executing edif2ngd -noa"distributed_arithmetic_fir_filter_spartan2_9_0_9e81e7a9fd77e066.edn""distributed_arithmetic_fir_filter_spartan2_9_0_9e81e7a9fd77e066.ngo"Release 10.1.03 - edif2ngd K.39 (nt)Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.INFO:NgdBuild - Release 10.1.03 edif2ngd K.39 (nt)INFO:NgdBuild - Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.Writing module to"distributed_arithmetic_fir_filter_spartan2_9_0_9e81e7a9fd77e066.ngo"...Loading design module "C:\Documents andSettings\Administrador\Desktop\hwcosim1\xflow\distributed_arithmetic_fir_filter_spartan2_9_0_9e81e7a9fd77e066.ngo"...Executing edif2ngd -noa"distributed_arithmetic_fir_filter_spartan2_9_0_62ef61469fa8be5d.edn""distributed_arithmetic_fir_filter_spartan2_9_0_62ef61469fa8be5d.ngo"Release 10.1.03 - edif2ngd K.39 (nt)Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.INFO:NgdBuild - Release 10.1.03 edif2ngd K.39 (nt)INFO:NgdBuild - Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.Writing module to"distributed_arithmetic_fir_filter_spartan2_9_0_62ef61469fa8be5d.ngo"...Loading design module "C:\Documents andSettings\Administrador\Desktop\hwcosim1\xflow\distributed_arithmetic_fir_filter_spartan2_9_0_62ef61469fa8be5d.ngo"...Gathering constraint information from source properties...Done.
Applying constraints in "jtagcosim_top.ucf" to the design...Resolving constraint associations...Checking Constraint Associations...Done...Checking Partitions ...
Checking expanded design ...ERROR:NgdBuild:604 - logical block 'jtag_iface' with type   'jtagcosim_iface_virtex' could not be resolved. A pin name misspelling can   cause this, a missing edif or ngc file, or the misspelling of a type name.   Symbol 'jtagcosim_iface_virtex' is not supported in target 'spartan2e'.WARNING:NgdBuild:443 - SFF primitive   'sysgen_hwcosim_iface/sysgen_dut/default_clock_driver_x0/xlclockdriver_1/clr_   reg/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp'   has unconnected output pinWARNING:NgdBuild:443 - SFF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/vali   d_pipe/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_comp'   has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[0].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[1].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[2].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[3].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[4].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[5].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[6].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[7].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[8].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[9].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[10].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[11].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[12].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/la   tency_test.reg/partial_one.last_srl17e/reg_array[13].fde_used.u2' has   unconnected output pinWARNING:NgdBuild:443 - SFF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/va   lid_pipe/latency_gt_0.fd_array[1].reg_comp/fd_prim_array[0].bit_is_0.fdre_com   p' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core   _instance/BU10517' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core   _instance/BU10523' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core   _instance/BU10529' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core   _instance/BU10535' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0/core_instance/core   _instance/BU10540' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/co   re_instance/BU3081' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/co   re_instance/BU3087' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/co   re_instance/BU3093' has unconnected output pinWARNING:NgdBuild:440 - FF primitive   'sysgen_hwcosim_iface/sysgen_dut/ifir_final2_x0/dafir_v9_0_1/core_instance/co   re_instance/BU3098' has unconnected output pin
Partition Implementation Status-------------------------------
  No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:  Number of errors:     1  Number of warnings:  22

One or more errors were found during NGDBUILD.  No NGD file will be written.
Writing NGDBUILD log file "jtagcosim_top.bld"...ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...    

 

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Xilinx Employee
Xilinx Employee
9,361 Views
Registered: ‎08-23-2008

Re: what is ngo build error and how it can be overcome

This error indicates that the modified core was not re-synthesized. Clean all the generated files in ISE and EDK and rerun implementation to work around this issue.

 

Cleanup in ISE shown in below screenshot:

 

ise_cleanup.JPG

 

Cleanup in EDK shown below:

 

edk_cleanup.JPG

 

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Newbie ambar686
Newbie
8,161 Views
Registered: ‎09-01-2013

Re: what is ngo build error and how it can be overcome

hi !! i was designing a full adder using two half adder using the following program in VHDL programming in Xilinx ISE 9.2i, but constantly i got the same error. please help me. any suggestion is acceptable.

the name of vhd file is fulladd.vhd.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fulladd is
Port ( a1 : in STD_LOGIC;
b1 : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
car : out STD_LOGIC);
end fulladd;

architecture fullad of fulladd is
component ha
port(a: in std_logic;
b: in std_logic;
sha,cha: out std_logic);
end component;
signal s1,c1,c2:std_logic;
begin
H1: ha port map(a1,b1,s1,c1);
H2: ha port map(s1,cin,sum,c2);
car<=c1 or c2;

end fullad;


the ERROR i m getting is:
ERROR:NgdBuild:604 - logical block 'H1' with type 'ha' could not be resolved. A
pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'ha' is not supported in target
'xa9500xl'.
ERROR:NgdBuild:604 - logical block 'H2' with type 'ha' could not be resolved. A
pin name misspelling can cause this, a missing edif or ngc file, or the
misspelling of a type name. Symbol 'ha' is not supported in target
'xa9500xl'.

 please help me...

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Community Manager
Community Manager
8,155 Views
Registered: ‎06-14-2012

Re: what is ngo build error and how it can be overcome

XST is considering ha as blackboxes. That means no logic is considered for that.

Have you added your RTL describing ha component?

 

In addition, if you have created netlists for ha componenet, use the sd switch in translate to specify the location for the IP netlist.

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