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Explorer
Explorer
3,874 Views
Registered: ‎04-28-2013

what's difference between LOCAL_CLOCK and REGIONAL_CLOCK?

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Hi,

  When I check my design's schematic of routed, I found that a register's Q_pin drives 3751's CK pins of other registers.

  the net connecting to the Q_pin's property is LOCAL_CLOCK. I want to know why a BUFG or BUFR is not inserted to the clock net to driver the 3581's CK pins  and I want to know the difference of the clock nets 's property between" LOCAL_CLOCK and REGIONAL_CLOCK"?

 

nonsense
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Historian
Historian
5,085 Views
Registered: ‎01-23-2009

Re: what's difference between LOCAL_CLOCK and REGIONAL_CLOCK?

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The tools do not auto-insert clock buffers on clock nets (with the possible exception of primary input clocks) - it is up to the user to insert the proper clock buffer, and hence choose the clock network that is going to be used.

 

If you are generating a "clock" from the output of a flip-flop then you need to tell the tool what you want to do with it:

  - no clock buffer: The clock is routed as a "Local clock" - it uses general fabric routing

     - while the tool tries to minimize it, a local clock will have large skew and long insertion latencies

  - BUFR: The output of the flip-flop is routed to the I/O column and into a BUFR. From there it the regional clock network fans it out to all the clocked elements in the current clock region, and (depending on the technology) the region above and below. This is a "regional clock". The skew is tightly controlled on this clock, and the insertion latency is relatively low, but it can only reach elements in a subset of the clock regions of the FPGA

  - BUFG: The output of the flip-flop is routed to the center of the FPGA, where it connects to a BUFG. From there the global clock distribution network fans it out to potentially all clocked elements in the FPGA. This also has low skew, but somewhat longer insertion latency

 

However, none of these are the preferred mechanism. If you really want to generate a clock inside the FPGA, it is best not to generate it in a flip-flop and then fan that out, but to use the BUFGCE or BUFHCE to gate an existing clock with a synchronous enable. This allows the clock to stay on dedicated clock resources all the way through the FPGA and not have the clock go on general fabric routing (which has unpredictable and uncontrollable delays).

 

Avrum

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2 Replies
Historian
Historian
5,086 Views
Registered: ‎01-23-2009

Re: what's difference between LOCAL_CLOCK and REGIONAL_CLOCK?

Jump to solution

The tools do not auto-insert clock buffers on clock nets (with the possible exception of primary input clocks) - it is up to the user to insert the proper clock buffer, and hence choose the clock network that is going to be used.

 

If you are generating a "clock" from the output of a flip-flop then you need to tell the tool what you want to do with it:

  - no clock buffer: The clock is routed as a "Local clock" - it uses general fabric routing

     - while the tool tries to minimize it, a local clock will have large skew and long insertion latencies

  - BUFR: The output of the flip-flop is routed to the I/O column and into a BUFR. From there it the regional clock network fans it out to all the clocked elements in the current clock region, and (depending on the technology) the region above and below. This is a "regional clock". The skew is tightly controlled on this clock, and the insertion latency is relatively low, but it can only reach elements in a subset of the clock regions of the FPGA

  - BUFG: The output of the flip-flop is routed to the center of the FPGA, where it connects to a BUFG. From there the global clock distribution network fans it out to potentially all clocked elements in the FPGA. This also has low skew, but somewhat longer insertion latency

 

However, none of these are the preferred mechanism. If you really want to generate a clock inside the FPGA, it is best not to generate it in a flip-flop and then fan that out, but to use the BUFGCE or BUFHCE to gate an existing clock with a synchronous enable. This allows the clock to stay on dedicated clock resources all the way through the FPGA and not have the clock go on general fabric routing (which has unpredictable and uncontrollable delays).

 

Avrum

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Explorer
Explorer
3,860 Views
Registered: ‎04-28-2013

Re: what's difference between LOCAL_CLOCK and REGIONAL_CLOCK?

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Thanks avrumw, I got it.

 

nonsense
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