01-30-2019 06:50 PM
I flopped the IDDR(#1 in the fig) output using FDCEs(#2 in the fig), but the tools select the FDCEs far from the IDDR, which cause setup violations. Why doesn't the tool choose the neighbor FDCEs, such as #3 in the fig?
01-30-2019 08:26 PM
First of all, you're not looking at the chip--you're looking at a graphical representation of the chip's major resources on a screen. And you can't see the connection dependencies and routing rules that must be followed by the tool, on the screen.
Secondly, if you think you can find a better placement for that item than the tool can, move it. Select it, then drag it to where you want it. Save that modified design and then see what happens. Give it a go; you've got nothing to lose.