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Voyager
Voyager
418 Views
Registered: ‎10-12-2016

why vivado throwing error if i use bufg and bufgctrl on same net ?

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Hi friends,

why vivado throwing error if i use bufg and bufgctrl on same net ?

BUF_BUFCTRL_Issue.png

Any help or suggestion is highly appreciated.

Thank You

S Sam

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1 Solution

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Moderator
Moderator
390 Views
Registered: ‎01-16-2013

Re: why vivado throwing error if i use bufg and bufgctrl on same net ?

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@ssampath

 

My suggestion from below forum post applies for this error too. Site "IOB_X0Y141" is not clock capable IO. You need to change it to clock capable IO to overcome the error message. 

https://forums.xilinx.com/t5/Implementation/placement-error-even-clock-from-IOB-to-PLL-of-same-region/m-p/928455/highlight/false#M23347

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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3 Replies
Moderator
Moderator
414 Views
Registered: ‎01-16-2013

Re: why vivado throwing error if i use bufg and bufgctrl on same net ?

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@ssampath

 

Can you share the complete error message?

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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Voyager
Voyager
400 Views
Registered: ‎10-12-2016

Re: why vivado throwing error if i use bufg and bufgctrl on same net ?

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Clock Rule: rule_cascaded_bufg
    Status: PASS
    Rule Description: Cascaded bufg (bufg->bufg) must be adjacent and cyclic
    U_POLARIS_CORE/U_carplay_mux/PHY12 (BUFGCTRL.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y30
    U_POLARIS_CORE/U_carplay_mux/PHY123 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y29

    Clock Rule: rule_cascaded_bufg
    Status: PASS
    Rule Description: Cascaded bufg (bufg->bufg) must be adjacent and cyclic
    U_UTMI_PHY1_CLK/clkout1_buf (BUFG.O) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
    U_POLARIS_CORE/U_carplay_mux/PHY12 (BUFGCTRL.I0) is provisionally placed by clockplacer on BUFGCTRL_X0Y30

    Clock Rule: rule_mmcm_bufg
    Status: PASS
    Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
    U_UTMI_PHY1_CLK/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y4
    U_UTMI_PHY1_CLK/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y28

    Clock Rule: rule_mmcm_bufg
    Status: PASS
    Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
    U_UTMI_PHY2_CLK/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X0Y5
    U_UTMI_PHY2_CLK/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y26

    Clock Rule: rule_gclkio_mmcm_1load
    Status: FAIL
    Rule Description: An IOB driving a single MMCM must both be in the same clock region if CLOCK_DEDICATED_ROUTE=BACKBONE
    is NOT set
    utmi_phy_1_clk60_IBUF_inst (IBUF.O) is locked to IOB_X0Y174
    U_UTMI_PHY1_CLK/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y4
    ERROR: The above is also an illegal clock rule
    Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets utmi_phy_1_clk60_IBUF] >

    Clock Rule: rule_gclkio_mmcm_1load
    Status: FAIL
    Rule Description: An IOB driving a single MMCM must both be in the same clock region if CLOCK_DEDICATED_ROUTE=BACKBONE
    is NOT set
    utmi_phy_2_clk60_IBUF_inst (IBUF.O) is locked to IOB_X0Y141
    U_UTMI_PHY2_CLK/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X0Y5
    ERROR: The above is also an illegal clock rule
    Workaround: < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets utmi_phy_2_clk60_IBUF] >

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Moderator
Moderator
391 Views
Registered: ‎01-16-2013

Re: why vivado throwing error if i use bufg and bufgctrl on same net ?

Jump to solution

@ssampath

 

My suggestion from below forum post applies for this error too. Site "IOB_X0Y141" is not clock capable IO. You need to change it to clock capable IO to overcome the error message. 

https://forums.xilinx.com/t5/Implementation/placement-error-even-clock-from-IOB-to-PLL-of-same-region/m-p/928455/highlight/false#M23347

 

--Syed

---------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

Did you check our new quick reference timing closure guide (UG1292)?
---------------------------------------------------------------------------------------------
0 Kudos