cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
ken32293355
Visitor
Visitor
909 Views
Registered: ‎03-21-2019

10G/25G Ethernet MAC generate bitstream error (license issue)

HI,

 

Weve tried to implement 10G/25G ethernet mac on xcku115-flvd1517-2-e. It can successfully run synthesis and implementation, however, when generating bitstream, we encountered an error:

 

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:

xxv_ethernet_0/inst/i_xxv_ethernet_0_top_0/i_xxv_ethernet_0_CORE (xxv_ethernet_0__xxv_ethernet_v2_4_0_mac_basekr_axis_hsec_cores)

If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

 

Our vivado version is 2018.1, and we have license keys as follows:licenseslicenses

 

Weve tried to search over the forum for solutions, and we found that many people tried resetting and regenerating the IP core. However, we regenerated IP, but still get the same error.

 

Is there any solution to this problem? Thanks!

0 Kudos
2 Replies
nupurs
Moderator
Moderator
863 Views
Registered: ‎06-24-2015

@ken32293355 

In this case you have enabled BASE-KR additional feature and for this you need an additional license file (xxv_ethernet_v2_4_0_mac_basekr). This is what is missing at your end.
If BASE-KR isn't needed here and was selected by mistake, then you can just unselect this option and that should then enable you a successful bitstream generation.

Thanks,
Nupur
--------------------------------------------------------------------------------------------
Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the 'thumbs-up' button).
anatoli
Moderator
Moderator
797 Views
Registered: ‎06-14-2010

Hello @ken32293355 ,

This topic is still open and is waiting for you.

If your issue is not solved yet, please reply in the thread, so that we can assist you with your issue.

However, if your question is answered and/or your issue is solved, please mark the response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then.  We appreciate your help.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal, take a look at our Versal Design Process Hub and our
Versal Blogs

------------------------------------------------------------------------------------------------
0 Kudos