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Participant abhijithcd
Participant
2,116 Views
Registered: ‎06-22-2017

Bitstream generation is not permitted error

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Hello,

 

I am getting this error trying to re-build a project done a year ago: 

 

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core (design_1_tri_mode_ethernet_mac_v9_0_3)

 

The project has a block design with AXI 1G/2.5G Ethernet Subsystem with AXI DMA. I guessed the IP evaluation license might have expired and tried to obtain a new evaluation license from Xilinx. As I couldn't find the AXI Ethernet Subsystem, I was redirected to Tri-mode Ethernet MAC IP and updated the same. I also updated the Ethernet 100BASEX/PCS/PMA or SGMII IP license. After that, I generated output products from the Block Diagram and performed OOC synthesis per block design. 

 

I am not able to understand the cause of this error. The old project was built under Vivado 2015.4 and I am also using the same version of Vivado. Does the evaluation license depend on the Vivado version we use?

 

Kindly help me to debug this error.

 

Thanks and Regards,

Abhijith

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1 Solution

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Moderator
Moderator
3,205 Views
Registered: ‎09-15-2016

Re: Bitstream generation is not permitted error

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Hi @abhijithcd

 

Thanks for providing the requisite information.

 

From the screenshots and Xinfo it is clear that you have the IP Evaluation license with the version limit till March 2018. But still you are getting the error. Can you try the below two suggestions.

1) The host id for your machine shows as 484d7ed90116,74da3849fe20 but host id for which the axi_ethernet_avb.lic and Temac_vivado_license.lic is c608bb1b.

I am not sure why VLM shows host id match. Can you try to generate the Evaluation license for host id 484d7ed90116 or 74da3849fe20?

2) Does your all licenses lies in the location C:\.Xilinx? Are there any other IPs in the design whose license in the location C:\.Xilinx work fine? Try moving the Ethernet IP license to some separate location and trying specifying in the VLM. Once this is done, regenerate the output products of the IP and run the design flow.

 

Hope this helps.

 

Regards

Rohit

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Regards
Rohit
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10 Replies
Moderator
Moderator
2,104 Views
Registered: ‎09-15-2016

Re: Bitstream generation is not permitted error

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@abhijithcd

 

Have you followed the steps mentioned in the below link?

https://www.xilinx.com/support/answers/58758.html

 

Can you also try creating the project from scratch and see if you see the same error?

 

Regards

Rohit

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Regards
Rohit
----------------------------------------------------------------------------------------------
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Participant abhijithcd
Participant
2,095 Views
Registered: ‎06-22-2017

Re: Bitstream generation is not permitted error

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@thakurr Thanks for the reply.

I will try creating the project from scratch and build. It would take some time. Meanwhile, I tried resetting the outputs again and checked the license status using the tcl commands.

 

set dp_ips [get_cells -hierarchical {bd_0_eth_mac*}]

foreach ips $dp_ips {report_property $ips}

 

I got the following output and couldn't determine the IP status.

 

Property Type Read-only Value
CLASS string true cell
C_1588 int false 0
C_ADD_FILTER int false 0
C_AT_ENTRIES int false 0
C_AVB int false 0
C_CNTR_RST int false 1
C_DEVICE_FAMILY_US int false 0
C_FAMILY string false virtex7
C_HALF_DUPLEX int false 0
C_HAS_2G5 int false 0
C_HAS_HOST int false 1
C_HAS_MDIO int false 1
C_HAS_STATS int false 0
C_IS_EVAL int false 1
C_MAC_SPEED string false TRI_SPEED
C_NUM_STATS int false 34
C_PFC int false 0
C_PHYSICAL_INTERFACE string false INTERNAL
C_RX_INBAND_TS_ENABLE int false 0
C_RX_VEC_WIDTH int false 79
C_STATS_WIDTH int false 64
C_S_AXI_ADDR_WIDTH int false 12
C_TX_INBAND_CF_ENABLE int false 0
C_TX_VEC_WIDTH int false 79
DONT_TOUCH bool false 1
FILE_NAME string true c:/Users/UserLab01/Documents/myworkspace/block_project/block_project.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0_block.vhd
HAS_2G5 int false 0
IS_BLACKBOX bool true 0
IS_DEBUGGABLE bool true 1
IS_ORIG_CELL bool true 0
IS_PRIMITIVE bool true 0
IS_SEQUENTIAL bool true 0
LINE_NUMBER int true 579
MAC_SPEED string false TRI_SPEED
NAME string true block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0/bd_0_eth_mac_0_core
NUM_INTERRUPTS int false 1
ORIG_REF_NAME string true tri_mode_ethernet_mac_v9_0_3
PARENT cell true block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0
PRIMITIVE_COUNT int true 2908
REF_NAME string true design_1_tri_mode_ethernet_mac_v9_0_3
Property Type Read-only Value
CLASS string true cell
FILE_NAME string true c:/Users/UserLab01/Documents/myworkspace/block_project/block_project.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/address_decoder.vhd
INIT hex false 2'h1
IS_BLACKBOX bool true 0
IS_DEBUGGABLE bool true 1
IS_ORIG_CELL bool true 0
IS_PRIMITIVE bool true 1
IS_SEQUENTIAL bool true 0
LINE_NUMBER int true 362
NAME string true block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/bd_0_eth_mac_0_core_i_1
PARENT cell true block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT
PRIMITIVE_COUNT int true 1
PRIMITIVE_GROUP string true LUT
PRIMITIVE_LEVEL enum true LEAF
PRIMITIVE_SUBGROUP string true others
PRIMITIVE_TYPE enum false LUT.others.LUT1
REF_NAME string true LUT1
STATUS enum true UNPLACED
Property Type Read-only Value
CLASS string true cell
FILE_NAME string true c:/Users/UserLab01/Documents/myworkspace/block_project/block_project.srcs/sources_1/bd/design_1/ipshared/xilinx.com/axi_lite_ipif_v3_0/hdl/src/vhdl/address_decoder.vhd
INIT hex false 4'h8
IS_BLACKBOX bool true 0
IS_DEBUGGABLE bool true 1
IS_ORIG_CELL bool true 0
IS_PRIMITIVE bool true 1
IS_SEQUENTIAL bool true 0
LINE_NUMBER int true 502
NAME string true block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/I_DECODER/bd_0_eth_mac_0_core_i_2
PARENT cell true block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/I_DECODER
PRIMITIVE_COUNT int true 1
PRIMITIVE_GROUP string true LUT
PRIMITIVE_LEVEL enum true LEAF
PRIMITIVE_SUBGROUP string true others
PRIMITIVE_TYPE enum false LUT.others.LUT2
REF_NAME string true LUT2
SOFT_HLUTNM string false soft_lutpair20216
STATUS enum true UNPLACED
Property Type Read-only Value
CLASS string true cell
FILE_NAME string true c:/Users/UserLab01/Documents/myworkspace/block_project/block_project.srcs/sources_1/bd/design_1/ip/design_1_axi_ethernet_0_0/bd_0/ip/ip_1/synth/bd_0_eth_mac_0_block.vhd
INIT hex false 4'h2
IS_BLACKBOX bool true 0
IS_DEBUGGABLE bool true 1
IS_ORIG_CELL bool true 0
IS_PRIMITIVE bool true 1
IS_SEQUENTIAL bool true 0
LINE_NUMBER int true 115
NAME string true block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/I_DECODER/bd_0_eth_mac_0_core_i_3
PARENT cell true block_1/design_1_i/Ethernet/axi_ethernet_0/U0/eth_mac/U0/axi4_lite_ipif/axi_lite_top/I_SLAVE_ATTACHMENT/I_DECODER
PRIMITIVE_COUNT int true 1
PRIMITIVE_GROUP string true LUT
PRIMITIVE_LEVEL enum true LEAF
PRIMITIVE_SUBGROUP string true others
PRIMITIVE_TYPE enum false LUT.others.LUT2
REF_NAME string true LUT2
SOFT_HLUTNM string false soft_lutpair20214
STATUS enum true UNPLACED

 

How could I check if the IP license is actually updated and being used? I could see that the IP versions are updated in the block diagram.

 

Thanks 

Abhijith

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Moderator
Moderator
2,092 Views
Registered: ‎09-15-2016

Re: Bitstream generation is not permitted error

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Hi @abhijithcd

 

You can open the VLM (Vivado License manager) from Vivado IDE. Go to Help-->Manage license. This will open VLM window as below, click of View license status. Also make sure you have correctly given the license file path as shown below:

 

MANAage_licensee.PNG

 

Regards

Rohit

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Rohit
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Participant abhijithcd
Participant
2,067 Views
Registered: ‎06-22-2017

Re: Bitstream generation is not permitted error

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@thakurr Thanks for the reply. 

 

The IP license I have is based on certificate and is node-locked to my hard-disk. After updating the TEMAC core, I checked the license status in "IP Catalog" it states as "eth_avb_endpoint@2015.4" and "tri_mode_eth_mac@2015.4", but in the xilinx license manager, I could see the IPs listed as version limit 2018.11 and exp. date March 2018.

 

I updated both the IP cores and checked in the license status in IP catalog. Here, it is still trying to refer @2015.4 versions.

I followed the solution mentioned in the below posts:

https://forums.xilinx.com/t5/Installation-and-Licensing/Licensing-help-with-the-Tri-Mode-Ethernet-MAC-v9-0-with-the/td-p/710473

https://forums.xilinx.com/t5/Networking-and-Connectivity/License-error-when-generating-bitstream-for-XAPP1178-v2-0/td-p/587799

 

I tried to remove the C:\XILINX\Vivado\2015.4\data\ip\core_licenses\Xilinx.lic as mentioned in the above post. After this, Vivado complains that the license is not found. But the new license is present in C:\.Xilinx folder which is not being read.

 

Could you please tell me what is going wrong? Am I missing any step?

 

Thanks,

Abhijith

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Moderator
Moderator
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Registered: ‎09-15-2016

Re: Bitstream generation is not permitted error

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Hi @abhijithcd

 

Can you share the below requisite information:

1)license file for IP evaluation license.

2) Xinfo file which can be generated by running the below command in the tcl console:

report_environment -file <file_path>env.txt

3) Screen shot of VLM showing the IP status. 

4) Screen shot of VLM showing manage license search path.

 

I doubt the tool is picking Design linking license for IP for which bitstream is not permitted.Design-Linking license for a LogiCORE IP Core is an evaluation license key that allows you to run through the entire design flow and perform both pre- and post-implementation simulation. However, you cannot generate bitstreams for designs that contain LogiCORE IP Cores enabled by a Simulation Only license. Have you correctly installed the new Evaluation license for IP?

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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Participant abhijithcd
Participant
2,040 Views
Registered: ‎06-22-2017

Re: Bitstream generation is not permitted error

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@thakurr Thank you. I even tried to re-install Vivado to remove any caches present. The error still persists.

 

Kindly find the attached zip folder for the requested parameters.

 

Thanks,

Abhijith

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Moderator
Moderator
3,206 Views
Registered: ‎09-15-2016

Re: Bitstream generation is not permitted error

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Hi @abhijithcd

 

Thanks for providing the requisite information.

 

From the screenshots and Xinfo it is clear that you have the IP Evaluation license with the version limit till March 2018. But still you are getting the error. Can you try the below two suggestions.

1) The host id for your machine shows as 484d7ed90116,74da3849fe20 but host id for which the axi_ethernet_avb.lic and Temac_vivado_license.lic is c608bb1b.

I am not sure why VLM shows host id match. Can you try to generate the Evaluation license for host id 484d7ed90116 or 74da3849fe20?

2) Does your all licenses lies in the location C:\.Xilinx? Are there any other IPs in the design whose license in the location C:\.Xilinx work fine? Try moving the Ethernet IP license to some separate location and trying specifying in the VLM. Once this is done, regenerate the output products of the IP and run the design flow.

 

Hope this helps.

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

Participant abhijithcd
Participant
2,011 Views
Registered: ‎06-22-2017

Re: Bitstream generation is not permitted error

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@thakurr

Thank you for being patient with my queries and all the answers.

The Host ID is tied to the Harddisk number and hence is c608bb1b. I will check with the NIC host ID once. 

 

I changed the IP location to a custom folder only with those 4 custom IP licences. I have removed the generic Xilinx.lic and XilinxFree.lic. The License manager still detects the 2018 versions. But in Vivado IP catalog, I still see the versions tied to 2015.4. Can't understand where it is taking those versions from. But If I open the IP, I could see at the bottom that the "Hardware_Evaluation IP license available" Attaching screenshots for reference.

 

Thanks,

Abhijith

License_status.PNG
old_license.PNG
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Moderator
Moderator
2,002 Views
Registered: ‎09-15-2016

Re: Bitstream generation is not permitted error

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Hi @abhijithcd

 

>>But in Vivado IP catalog, I still see the versions tied to 2015.4. Can't understand where it is taking those versions from. But If I open the IP, I could see at the bottom that the "Hardware_Evaluation IP license available" Attaching screenshots for reference.

 

Don't get confused with what you are seeing in the IP catalog. IP catalog shows all the IPs you have for Vivado even if you don't have license for the IP. Since you are using Vivado 2015.4 hence it is showing like that in the IP catalog.

 

Try generating the license for the correct hostid as mentioned before.

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

Participant abhijithcd
Participant
816 Views
Registered: ‎06-22-2017

Re: Bitstream generation is not permitted error

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@thakurr

 

The bitstream is generating fine now. 

I would like to mention a few probable steps which might have led to the working just as a reference.

 

1. I deleted the cache files of the project and also the cache files of Vivado.

2. Removed all the license references and created a new folder with only required licenses and linked it with the license manager.

3. As mentioned by you, even though the IP catalog was showing license version as @2015.4, on opening the IP customization window it was showing "Hardware_Evaluation IP License available". That was a cue that new license was being referenced.

 4. I tried this before changing the Host ID to NIC. So the IPs are working with the Hard Disk ID itself.

Once again thanks for all the help.

 

Regards,

Abhijith