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Visitor mskim
Visitor
1,113 Views
Registered: ‎05-09-2018

Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi,

 

 

I'm new user of ZEDboard and my question might be a beginner question. I' sorry for that.

 

I get the following error when trying to generate a .bit file for an example design using the Axi-USB2-Device IP core.

 

 

 

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:

design_1_i/axi_usb2_device_0/U0 (axi_usb2_device)

If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

 

 

 

I have looked at previous Answer records which recommend resetting and Regenerating output products. This hasn't worked for me. And my license is correct.

 

What I cannot understand is: I have a project that contains the usb core and that will complete correctly already.(https://www.xilinx.com/support/documentation/application_notes/xapp891-7...) However my example design project that contains the same core will not generate a bit file.

 

I am using Vivado 2018.1.

 

 

 

Any help would be greatly appreciated.

 

Thanks

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Moderator
Moderator
1,004 Views
Registered: ‎06-14-2010

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hello @mskim,

 

To determine if your IP core was generated with the correct license run:

 

get_property used_license_keys [get_ips <hdmi core name>]

 

e.g.

 

get_ips

 

>tri_mode_ethernet_mac_0

 

 

get_property used_license_keys [get_ips tri_mode_ethernet_mac_0]

 

>{{simulation {tri_mode_eth_mac@2015.04 design_linking} {eth_avb_endpoint@2015.04 hardware_evaluation}} {synthesis {tri_mode_eth_mac@2015.04 design_linking} {eth_avb_endpoint@2015.04 hardware_evaluation}} {changelog {tri_mode_eth_mac@2015.04 design_linking} {eth_avb_endpoint@2015.04 hardware_evaluation}} {instantiation_template {tri_mode_eth_mac@2015.04 design_linking} {eth_avb_endpoint@2015.04 hardware_evaluation}}}

 

Also, in Vivado ->Reports->Report IP Status, please generate and share with us what you see. This should show all of the IPs found in your design and what licenses are available for each. If you see Design_Linking instead of Harware or Purchased, then Vivado can't detect the location of your valid license file.

I would suggest opening your Vivado License Manager and setting the XILINXD_LICENSE_FILE environment variable to point to the folder where you have stored your IP Core licenses.

 

 

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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3 Replies
Community Manager
Community Manager
1,028 Views
Registered: ‎05-08-2017

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hi @mskim,

 

Can you perform a report IP status on the core and report the results?

 

If by chance you have the other project open but only one seat on the license, that could be not allowing your example project IP to be supported by the license.

 

Thank you,
Devin

 

 

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Moderator
Moderator
1,005 Views
Registered: ‎06-14-2010

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hello @mskim,

 

To determine if your IP core was generated with the correct license run:

 

get_property used_license_keys [get_ips <hdmi core name>]

 

e.g.

 

get_ips

 

>tri_mode_ethernet_mac_0

 

 

get_property used_license_keys [get_ips tri_mode_ethernet_mac_0]

 

>{{simulation {tri_mode_eth_mac@2015.04 design_linking} {eth_avb_endpoint@2015.04 hardware_evaluation}} {synthesis {tri_mode_eth_mac@2015.04 design_linking} {eth_avb_endpoint@2015.04 hardware_evaluation}} {changelog {tri_mode_eth_mac@2015.04 design_linking} {eth_avb_endpoint@2015.04 hardware_evaluation}} {instantiation_template {tri_mode_eth_mac@2015.04 design_linking} {eth_avb_endpoint@2015.04 hardware_evaluation}}}

 

Also, in Vivado ->Reports->Report IP Status, please generate and share with us what you see. This should show all of the IPs found in your design and what licenses are available for each. If you see Design_Linking instead of Harware or Purchased, then Vivado can't detect the location of your valid license file.

I would suggest opening your Vivado License Manager and setting the XILINXD_LICENSE_FILE environment variable to point to the folder where you have stored your IP Core licenses.

 

 

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
-------------------------------------------------------------------------
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-------------------------------------------------------------------------

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Moderator
Moderator
945 Views
Registered: ‎06-14-2010

Re: Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted

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Hello @mskim,

 

This topic is still open and is waiting for you.

 

If your question is answered and/or your issue is solved, please mark a response that resolved your issue, as Accepted Solution (more info on this can be found here: https://forums.xilinx.com/t5/help/faqpage/faq-category-id/solutions#solutions). This way, the topic can be completed then. 

 

If this is not solved/answered, please reply in the thread.

 

Thanks in advance and have a great day.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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