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Visitor
Visitor
225 Views
Registered: ‎04-04-2019

Design Linking does not allow configuration and/or example design generation

I would like to be able to examine the example design for IP cores that require license to generate. I see that some have design linking included, but when I generate the IP it does not let me configure or generate an example design.

I was specifically trying to generate the DisplayPort example design. I added this IP to a block design but if I customize the core when it exits the dialog it fails to save the settings. I also tried to generate the example design and it also failed in a similar manner. I was hoping to examine the example design before my IT department is able to add an Evaluation license to the floating license.

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎07-16-2008

回复: Design Linking does not allow configuration and/or example design generation

What error did you encounter? Design linking license shouldn't prevent the generation of IP Example Design.

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Visitor
Visitor
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Registered: ‎04-04-2019

回复: Design Linking does not allow configuration and/or example design generation

The IT department have added the Hardware Evaluation license. It no longer reports failures. It previously indicated in the IP configuration GUI that is located a design linking license, but when I configured the IP it failed on GUI exit indicating something was locked. I also tried right clicking on the IP core inside IPI and selected "Generate example design" it failed in a similar way.

I have disconnected from the server and added the IP to IPI again. It provides the errors below, but if I open the GUI (snapshot attached) is states "Design linking license available".

startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:dp_tx_subsystem:2.1 dp_tx_subsystem_1
WARNING: [IP_Flow 19-2162] IP 'displayport_v7_0_11_rs_decoder_v9_0_16_viv' is locked:
* IP 'displayport_v7_0_11_rs_decoder_v9_0_16_viv' requires one or more mandatory licenses but no valid licenses were found. However license checkpoints may prevent use of this IP in some tool flows.
ERROR: [Common 17-107] Cannot change read-only property 'CONFIG.aclken'.
Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2019.1/data/ip/xilinx/displayport_v7_0/ttcl/rs_decoder_elaborate.xit': ERROR: [Common 17-107] Cannot change read-only property 'CONFIG.aclken'.
Resolution: Please refer to Vivado Properties Reference Guide (UG912) for more information on setting properties.

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'dp_tx_subsystem_1/inst/dp'. Failed to generate 'Elaborate Sub-Cores' outputs:
ERROR: [BD 41-145] Parameter lnk_clk.CLK_DOMAIN not found on block dp
ERROR: [BD 41-145] Parameter common_qpll_clk_out.CLK_DOMAIN not found on block dp
ERROR: [BD 41-145] Parameter common_qpll_ref_clk_out.CLK_DOMAIN not found on block dp
ERROR: [BD 41-145] Parameter lnk_clk_ibufds_out.CLK_DOMAIN not found on block dp
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
CRITICAL WARNING: [IP_Flow 19-1747] Failed to deliver file 'c:/Xilinx/Vivado/2019.1/data/ip/xilinx/dp_tx_subsystem_v2_1/elaborate/bd.xit': ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

ERROR: [IP_Flow 19-167] Failed to deliver one or more file(s).
ERROR: [IP_Flow 19-3541] IP Elaboration error: Failed to generate IP 'dp_tx_subsystem_1'. Failed to generate 'Elaborate BD' outputs: Failed to elaborate IP.
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.
endgroup

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Moderator
Moderator
112 Views
Registered: ‎06-14-2010

回复: Design Linking does not allow configuration and/or example design generation

Hello @bdering ,

This error due to the fact that the tool can't detect your rs_decoder license file.

Can you please open your Vivado and do report_ip_status and then see if a valid license is listed for this  IP core in the list?

You should see Purchased or Hardware_Eval and not e.g. Design Entry (see my example screenshot below for one of the Video IP Core). Please send me a similar screenshot that you see at your end.

image.png

 

If you see Purchased or Hardware_Eval and no Design Linking, then right click on the IP Core and selected “reset output products” and then “Regenerate output products” and then re-run synth, Implementation and generate bitstream. Then see if this time your bitstream still fails with the same error message or not.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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