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Newbie williamlu97
Registered: ‎01-18-2019

Having trouble connecting to Virtex-7 FPGA

I'm currently using an eval board from Analog Devices, the ADS7-V2EBZ eval board.  It is based off the Xilinx Virtex-7 XC7VX330T-3FFG1157E FPGA.  I downloaded Vivado and when i'm creating a project i can't find the exact part for this board.  When i choose one that's similar I'm unable to get past the Code Synthesis step and it give tells me that there's something wrong with my license.  Do i need to buy a specific license to use with this board?

Also how do i get past the Bitstream generation step?  When i choose a different part just to test my code i get an error on the bitstream generation part where it tells me i haven't defined the I/O ports.  Is there a way to get past this step?

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3 Replies
Scholar u4223374
Registered: ‎04-26-2015

Re: Having trouble connecting to Virtex-7 FPGA

You will need a Vivado Design Edition license; the free WebPack license does not support the Virtex chips.


If bitstream generation is complaining that you haven't defined your I/O ports, the obvious question is whether you have actually defined your I/O ports. Have you?

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Newbie williamlu97
Registered: ‎01-18-2019

Re: Having trouble connecting to Virtex-7 FPGA

I have not defined my I/O ports, i'm not sure how to define ports.  Are there any resources for beginner FPGA coders that i can look at?

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Xilinx Employee
Xilinx Employee
Registered: ‎06-13-2018

Re: Having trouble connecting to Virtex-7 FPGA

Hi @williamlu97 :

You must have a license to use this device. 

Vivado WebPACK Tool does not support Virtex-7 FPGA. That's why you are getting a license error in code synthesis step. You will need Vivado Design Suite Editions (latest are 2018.2 or 2018.3) that support Virtex-7 devices. 

You will only be able to use below devices with Webpack Edition 2018.3:

Supported Device18.3.PNG

You can check this link for reference :



You can refer to Vivado Design Suite Tutorial 1.Using Constraints (UG945) and 2.Design Flows Overview (UG888) to learn about complete Vivado Project flow untill Bitstream generation. 

1. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug945-vivado-using-constraints-tutorial.pdf

2. https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug888-vivado-design-flows-overview-tutorial.pdf






If you find this information useful, please mark it "accept as solution"


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