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Hvae a Lite version License apparently. But code doues not simulate for 14.7 ise design suite

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ISim P.20131013 (signature 0x7708f090)

----------------------------------------------------------------------

INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set.

INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set.

INFO:Security:68 - For more information or for assistance in obtaining

a license, please run the Xilinx License Configuration Manager

(xlcm or "Manage Xilinx Licenses".)

INFO:Security:68a - user is Sandeep, on host SANDEEP-PC.

INFO:Security:15 - A feature for ISIM was found but is for the wrong hostid.

ERROR:Security:14 - No feature was available for 'ISIM'.

 

Invalid host.

The hostid of this system does not match the hostid

specified in the license file.

Feature: ISIM

Hostid: DISK_SERIAL_NUM=a683ff30

License path: C:/.Xilinx\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE\/coregen/core_licenses\Xilinx.lic;C:\Xilinx\14.7\ISE_DS\ISE\/coregen/core_licenses\XilinxFree.lic;C:\Xilinx\14.7\ISE_DS\EDK/data/core_licenses\Xilinx.lic;

FLEXnet Licensing error:-9,57

For further information, refer to the FLEXnet Licensing documentation,

available at "www.flexerasoftware.com".

----------------------------------------------------------------------

WARNING: A full ISim License cannot be checked out due to the issues listed above. Please use Xilinx License Configuration Manager to fix these issues in order to check out a full ISim license.

WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.

This is a Lite version of ISim.

ERROR: FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.ERROR: The simulation failed to launch for the following reason:

The Simulation shut down unexpectedly during initialization. Please review the ISim log (isim.log) for details.

Please shut down ISim and retry the simulation. If the problem persists, please contact Xilinx support.

 

 

The above is the error i get and i am not able to simulate my code due to this error. 

The code simulates fine for a lower dimension input but when i increase the input dimension i get the above error message.

I have also attached the .lic fiile for any reference.

Thanks for the help.

 

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Moderator
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Registered: ‎07-01-2015

Hi @sandy_1022,

 

Please try the following steps:

1. Add sources

2. Add or create simulation sources

3. Add files

4. Select All files

5. Add text1.txt and text2.txt

 

Use 

$readmemb("text1.txt",matx);
$readmemb("text2.txt",maty);

Please let me know the outcomes of the above steps.

 

Thanks,
Arpan

Thanks,
Arpan
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Explorer
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Hi @syedz @arpansur 

 

Can you please hekp me on this onoe too.

 

Thank you so much

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Hi @sandy_1022,

 

 

Set the license path in XILINXD_LICENSE_PATH.

Click on "Set" after setting the license path.

 

Thanks,
Arpan

Thanks,
Arpan
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Hi @arpansur

Thanks for your reply. 

But i still seem to have the same problem. My code works fine if my input text file data is of lower range. But if i increase the input range anything above a 4X4 matrix i'm stiI getting the following error. 

 

Regards,

Sandy

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Registered: ‎07-01-2015

Hi @sandy_1022,

 

Please go through following link:

https://forums.xilinx.com/t5/Simulation-and-Verification/ISim-11-1-Lite-version-quot-Simulator-is-doing-circuit/td-p/39375

 

If you are using antivirus then try once simulating by disabling the antivirus.

 

Is it possible to verify the same in Vivado latest version?

 

Thanks,
Arpan

 

Thanks,
Arpan
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Explorer
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Registered: ‎01-01-2016

@arpansur

 

I will try that and let you know. 

Apparently i'm having the same trouble with Vivado as well as i have mentioned in my other post, though i have a full version license for it which i got from the Artix 7 FPGA board. 

Please find the link for your reference.

 

https://forums.xilinx.com/t5/Welcome-Join/Have-a-original-vivado-lic-file-Still-license-error-occurs/m-p/673617#M33195

 

Also do i need to change anything in my verilog code in order to use it in Vivado? Because i have designed it in ISE design Suite 14.7 and now i want to implement it on FPGA using Vivado 2015.4

 

Thank you so much for your help!

Sandy

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Explorer
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Registered: ‎01-01-2016

Hi @arpansur

 

I tried running the simulation by disabling the anitvirus and i am still having the same problem running my code. Also my code works for lower dimension input data. and i checked for any infinite loops as well and i don't have any. 

 

Kindly help me on this,

Sandy

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Explorer
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Registered: ‎01-01-2016

@arpansur

@pulim

@drjohnsmith

@austint

@Anonymous

 

Any help is appreciated guys. I've spent a lot of time googleing it and i'm left clueless as to why i'm facing this problem

 

Thanks a lot,

Sandy

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Hi @sandy_1022,

 

If possible please share your code here.

 

Thanks,
Arpan

Thanks,
Arpan
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Teacher
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Registered: ‎07-09-2009
Was iSim lite limited in the number of nodes it could cope with ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Registered: ‎06-24-2015

Please share the isim.log file generated for this project.
Also, share your code here.
In this Isim lite version, when your design plus test bench exceeds 50,000 lines of HDL code, the simulator begins to derate the performance of the simulator for that invocation. It is possible that we might not see the same crash in ISIM full version, so we need to check that.

Thanks,
Nupur
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Hi @nupurs

@drjohnsmith

@arpansur

 

Please find the code attached. 

Please find isim file attached. 

Also plese find the console snip which i get when i run a 3X3 matrix. I get proper output. 

But when i run any matrix dimension above 4X4 i get the errors which i have posted before.

 

Any help is appreciated.

Thanks a lot,

Sandy

 

 

 

`timescale 1ns / 1ps
//`define X_trc (WIO>=2)? (WIO-2+frcL) : frcL

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:52:24 11/28/2015
// Design Name:
// Module Name: gschmidt
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////// //////////////////////////
module gschmidt # (parameter WI=35,
WF=25,
size1=9, //row1 * col1
act_size=2, //do not change for any iter value
row2=3,
iter=5, //no. of iterations
a_iter=iter,
b_iter=a_iter+iter+1,
c_iter=b_iter+iter+1,
prod_x=size1*act_size, // product of size of 1st matrix(row1*col1)
index=row2*act_size) //index factor between the matrix(col1 or row2)


(input RST, CLK,
output ADDER_ERROR,
output reg signed [10:0] z,act_maty,act_matx,
output reg signed [WI+WF-1:0] final_out2,
output reg signed [WI+WF-1:0] final_out1,
output reg signed [WI+WF-1:0] final_out);
reg signed [WI+WF-1:0] matx [size1-1:0];
reg signed [WI+WF-1:0] maty [8:0];
reg signed [WI+WF-1:0] maty1 [row2-1:0];
reg signed [WI+WF-1:0] maty2 [row2-1:0];
reg signed [WI+WF-1:0] maty3 [row2-1:0];
reg signed [WI+WF-1:0] maty4 [row2-1:0];

wire signed [WI+WF-1:0] x1[size1-1:0];
wire signed [WI+WF-1:0] mul[size1-1:0];
wire signed [WI+WF-1:0] a[index-1:0];
wire signed [WI+WF-1:0] b[index-1:0];
wire signed [WI+WF-1:0] c[index-1:0];
wire signed [WI+WF-1:0] a1[index-1:0];
wire signed [WI+WF-1:0] b1[index-1:0];
wire signed [WI+WF-1:0] c1[index-1:0];
wire signed [WI+WF-1:0] g[row2-1:0];
wire signed [WI+WF-1:0] h[row2-1:0];
wire signed [WI+WF-1:0] h1[row2-1:0];
wire signed [WI+WF-1:0]finout[row2-1:0];
wire [WI+WF-1:0]ADDER_OVERFLOW; //,ADDER_ERROR_H2,ADDER_ERROR_H3,ADDER_ERROR_HLP,ADDER_ERROR_HHP;

reg [15:0]count;

initial begin
$readmemb("text1.txt",matx);
$readmemb("text2.txt",maty);
end

 

wire [19:0] x2 =20'b0;
integer m,w,w1;


genvar i,j,o,pca_cols,p,q,r,s,u,v;

generate


for (i=0;i<size1-1;i=i+row2) //increment factor is the index factor //middle factor is the product of size of first matrix
begin:PIPE_IIR_DF1
for (j=0;j<row2;j=j+1) //upto index factor
begin:PIPE_IIR_DF11

fp_Mult # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) m1(.RST(RST),.in1(matx[j+i]), .in2(((count==0 || count==a_iter+1 || count==b_iter+1)?maty[j]:maty1[j])),.out(mul[i+j]));
fp_Add # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) a1(.RST(RST),.in1(mul[i+j]), .in2(((j==0)?x2:x1[j+i-1])),.out(x1[j+i]),.OVF(ADDER_OVERFLOW[i+j]));

 

end
end

for (o=0;o<row2;o=o+1)
begin:PIPE_IIR_DF12
assign finout[o]=x1[((row2*(o+1))-1)];
end
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

for(q=0;q<row2+1;q=q+row2) //should run only twice
begin:PIPE_IIR_DF13
for (p=0;p<row2;p=p+1)
begin:PIPE_IIR_DF14

fp_Mult # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) m2(.RST(RST),.in1(((q==0)?maty2[p]:finout[p])), .in2(maty2[p]),.out(a[p+q]));
fp_Add # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) a2(.RST(RST),.in1(a[p+q]),.in2(((p==0)?x2:b[p+q-1])), .out(b[p+q]),.OVF(ADDER_OVERFLOW[p+q]));

fp_Mult # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) m3(.RST(RST),.in1(((q==0)?b[row2-1]:b[2*row2-1])), .in2(((q==0)?finout[p]:maty2[p])),.out(c[p+q]));

end
end

for (o=0;o<row2;o=o+1)
begin:PIPE_IIR_DF15
fp_Sub # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) s1(.RST(RST),.in1(c[o]),.in2_sub(c[o+row2]), .out( h[o]),.OVF(ADDER_OVERFLOW[o]));
end

for (r=0;r<row2+1;r=r+row2)
begin:PIPE_IIR_DF16
for (s=0;s<row2;s=s+1)
begin:PIPE_IIR_DF117

fp_Mult # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) m4(.RST(RST),.in1(((r==0)?maty3[s]:h[s])), .in2(maty3[s]),.out(a1[s+r]));
fp_Add # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) a3(.RST(RST),.in1(a1[s+r]), .in2(((s==0)?x2:b1[s+r-1])), .out(b1[s+r]),.OVF(ADDER_OVERFLOW[s+r]));

fp_Mult # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) m5(.RST(RST),.in1(((r==0)?b1[row2-1]:b1[2*row2-1])), .in2(((r==0)?h[s]:maty3[s])),.out(c1[s+r]));

end
end

for (o=0;o<row2;o=o+1)
begin:PIPE_IIR_DF18
fp_Sub # (.WI1(WI),.WF1(WF),.WI2(WI),.WF2(WF),.WIO(WI),.WFO(WF)) s2(.RST(RST),.in1(c1[o]), .in2_sub(c1[o+row2]), .out(h1[o]),.OVF(ADDER_OVERFLOW[o]));
end


always @(posedge CLK) begin


if(RST)
final_out<=0;
else
final_out<=h1[0];
final_out1<=h1[1];

end

endgenerate

always @(posedge CLK) begin
if(RST)
count<=-1;

else
begin

if (count<a_iter) begin
for (m=0;m<row2;m=m+1) begin
maty1[m]<=finout[m];
maty2[m]<=finout[m];
end
count<=count+1;

end
else if (count<b_iter) begin
if (count==a_iter) begin
for (m=0;m<row2;m=m+1) begin
maty2[m]<=maty1[m];
end
end

for (m=0;m<row2;m=m+1) begin
maty1[m]<=h[m];
end

for (w=0;w<row2;w=w+1)begin
maty[w]<=maty[w+3];
end
if (count==b_iter-1) begin
for (m=0;m<row2;m=m+1) begin

maty3[m]<=h[m];
end
end
count<=count+1;

end
else if (count<c_iter) begin
count<=count+1;


for (w1=0;w1<row2;w1=w1+1) begin
maty[w1]<=maty[w1+6];
end

for (m=0;m<row2;m=m+1) begin
maty1[m]<=h1[m];

end

if (count==c_iter-1) begin
for (m=0;m<row2;m=m+1) begin
maty4[m]<=h1[m];
end
end


end
else begin

count<=0;

end
end

end
// working ends here

endmodule

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Hi @sandy_1022,

 

Please share text1.txt and text2.txt. Also the Add, Sub, Mult modules.

 

Thanks,
Arpan

Thanks,
Arpan
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Explorer
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Hi @arpansur

 

Please find the files attached. 

Also i checked it with a full version of ISE Design Suite and i'm still having the same error. Now i'm thinking there might be a problem with my code. 

 

 

Thanks,

sandy

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please change "size1" to 100 and "row2" to 10 and check the code.
Both are found in my actual code in my previous comment.
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Hi @sandy_1022,

 

I am seeing crash in ISE. 

I am not sure about the logic used in your design. But in Vivado I am not seeing crash.

 

Thanks,
Arpan

Thanks,
Arpan
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Hi @arpansur

 

Thank you so much for checking the code for me. So your saying the code is running perfectly fine in Vivado and not on ISE. How is it possible? Anyway i'm glad the code is working. 

 

If i can install the Webpack and get my code running on Vivado, then i'll be forever greatful to you. 

 

 

Thanks,

Sandy

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Hi @sandy_1022,

 

Please try in Vivado and let us know if you are able to simulate the deisgn.

 

Thanks,
Arpan

Thanks,
Arpan
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Hi @arpansur

 

I was finally able to run the simulation on VIvado without getiing it crashed. Thanks a lot for all your help. 

 

However,i'm getting certain errors in VIVADO which didn't exist when i was running the same in ISE 14.7 for a lower dimension input data. 

For EX: the text file input is not reading in the simulation, though i have the text files in the same directory as that of the project. Can you please help me through that. 

 

Also please find my Test bench attached. I'm having certain errors which didn't occur in ISE. Can you suggest me any possible changes? You can just use it without changing any parameters.

 

 

Thanks again for all the support,

Sandy

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@arpansur

 

Hi , do you know why I'm getting that error ? can you please help me in this ?

 

Thanks,

Sandy,

 

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Hello @sandy_1022

 

Provide the complete path of the file instead of just file name because the current working directory is different from the files location.

 

Thanks,

Vinay

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Hi @sandy_1022,

 

Can you please verify if the path is correct?

It seems it's E:/vivado/gramschmidt/text1.txt

 

Use the above path in instead of only text1.txt and text2.txt.

$readmemb("text1.txt",matx);
$readmemb("text2.txt",maty);

 

Thanks,
Arpan

Thanks,
Arpan
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Hi @vuppala

 

As you can see from my previous post, the vivado file and the two text files i'm reading are in the same directory.

 

They are : 

E:\vivado\gramschmidt

 

Thanks,

Sandy

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Hi @arpansur

 

I tried your suggestion. I am still getting the same error. 

 

WARNING: File E:/vivado/gramschmidt/text1.txt referenced on E:/vivado/gramschmidt/gramschmidt.srcs/sources_1/new/gschmidt.v at line 74 cannot be opened for reading. Please ensure that this file is available in the current working directory.
xsim: Time (s): cpu = 00:00:02 ; elapsed = 00:00:08 . Memory (MB): peak = 2191.766 ; gain = 0.000
INFO: [USF-XSim-96] XSim completed. Design snapshot 'gschmidt_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:02 ; elapsed = 00:00:41 . Memory (MB): peak = 2191.766 ; gain = 0.000

 

 

 

 

How can i know the working directory? From my previous post snip, you can see that both the Vivado file and the text files are in the same folder. Why am i still getting this error?

 

Thanks,

Sandy

 

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Hi@arpansur

Hi @vuppala

 

Any solution for me please?

 

Thanks,

Sandy

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Hi @sandy_1022,

 

I tried to reproduce this issue but could not.

 

Thanks,
Arpan

Thanks,
Arpan
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Hi @arpansur

 

Thanks a lot for trying it out. So what is the solution? or is there any other alternative? because i somehow have to read the inputs from the text file.

 

Thanks,

Sandy

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Hi @arpansur

 

Also from your previous post, where you have posted a snap of the simulation, i see that the two text files are being read by vivado and they are green. matx and maty are the two text file inputs. 

How were you able to run it then?

 

Thanks,

Sandy

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Hi @sandy_1022,

 

Are you simulating gschmidt.v?

If not please simulate gschmidt.v and let me know.

Have you made any changes in gschmidt.v?

 

Thanks,
Arpan

Thanks,
Arpan
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Hi @arpansur

 

Yes i am simulating the UUT(gschmidt.v) and not the test bench file. 

And just FYI. I also get this warning message in addition : 

 

 

Thanks,

Sandy

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