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Observer
Observer
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Registered: ‎08-19-2019

Is Vivado HLS edition free now?

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I download VIvado HLx edition, and click all options during installation. After installing, I found there is also a Vivado HLS downloaded in my Desktop (I use Ubuntu), and Vivado HLS edition doesn't need license to run code, but Vivado HLx edition needs. Is the Vivado HLS edition totally free to use now?

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Advisor
Advisor
730 Views
Registered: ‎04-26-2015

You're a little bit confused about tools.

Vivado HLS is not an edition, it's a separate tool. It converts C/C++ code (or something close to that) into Verilog/VHDL, but it cannot produce an FPGA bitstream. No separate license is required, it just uses whatever license Vivado is using.

Vivado is the tool that turns Verilog/VHDL into an FPGA bitstream. It does require a license, although for all the small devices there's a free "WebPack" license that gets generated automatically and gives you virtually all the functionality of the full Design Edition (all you miss out on is Partial Reconfiguration, which is no great loss).

Vivado HLx is the name for both of the above tools packaged together.

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Advisor
Advisor
731 Views
Registered: ‎04-26-2015

You're a little bit confused about tools.

Vivado HLS is not an edition, it's a separate tool. It converts C/C++ code (or something close to that) into Verilog/VHDL, but it cannot produce an FPGA bitstream. No separate license is required, it just uses whatever license Vivado is using.

Vivado is the tool that turns Verilog/VHDL into an FPGA bitstream. It does require a license, although for all the small devices there's a free "WebPack" license that gets generated automatically and gives you virtually all the functionality of the full Design Edition (all you miss out on is Partial Reconfiguration, which is no great loss).

Vivado HLx is the name for both of the above tools packaged together.

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Observer
Observer
673 Views
Registered: ‎08-19-2019

Thanks for sharing! It is very clear for understanding these tools. Moreover, I notice that by running high-level synthesis by C/C++/SystemC on Vivado HLS, there are Verilog / VHDL codes automatically generated. Is this always a good generation which we could directly feed into Vivado and fabricate in FPGA?

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