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Explorer
Explorer
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Registered: ‎09-14-2018

KCU105 Example Design Write Bitstream ERROR

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I tried to recompile (in Vivado 2018.3) and generate the bit file from the KCU105 IP Integrator example design (rdf0313-kcu105-ipi-c-2017-3.zip ), but I got the write_bitstream ERROR.  Here is the message:

 

write_bitstream failed

ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:

system_i/axi_ethernet_0/inst/mac/inst/bd_4bad_mac_0_core (<encrypted cellview>).

If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.

 

It appears, it is related to the axi_ethernet  MAC license, but I am not certain. The IP was upgraded successfully.

Thank you

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Moderator
Moderator
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Registered: ‎06-14-2010

Re: KCU105 Example Design Write Bitstream ERROR

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Hello @arotenst ,

If you see Design_linking for your AXI 1G/2.5G Ethernet Subsystem, that is the reason for the licensing error you've shared in the original post.

Do you have a tri_mode_eth_mac IP Core license in place? Please note that you'd need a Tri-mode Ethernet Media Access Controller (TEMAC) license for this IP.

You can obtain a free Hardware Evaluation license for this IP from here: https://www.xilinx.com/products/intellectual-property/axi_ethernet.html

Here is a direct link for it: https://www.xilinx.com/member/forms/license-form.html?tab=CreateLicense&product=0451141

Once you have this license generated and installed, when you re-do report_ip_status, you should then see HW_Eval instead of Design_Linking, and if that is the case, right click on this IP and do reset and then regenerate output products for this IP first and then re-run Synthesis, Implementation and then generate Bitgen. Then see if you still seeing the same error or not.

Hope this helps.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-13-2018

Re: KCU105 Example Design Write Bitstream ERROR

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Hello @arotenst ,

Can you please check https://www.xilinx.com/support/answers/58758.html and follow the work-around mentioned in the AR.

Probably this will help you in resolving the issue.

Regards,

Naveen 

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Explorer
Explorer
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Registered: ‎09-14-2018

Re: KCU105 Example Design Write Bitstream ERROR

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Hello Naveen,

I see steps in AR# 57264 (for BD based design). I do not understand the steps.

1) Create a local Repository and add it to the Project. I did but why?

2)  Verify that the new IP is found in the IP catalog. Checked VLNV. But again why? What would it change? It is only one available IP.

3) Upgrade IP. How? An how a new repository path does with it?

Thank you.

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Moderator
Moderator
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Registered: ‎06-14-2010

Re: KCU105 Example Design Write Bitstream ERROR

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Hello @arotenst ,

Can you please open your Vivado and do report_ip_status and then see all of the IP Cores found in your design if a valid license is listed for each IP core in the list?

You should see Purchased and not e.g. Design Entry (see my example screenshot below for one of the Video IP Core). Please send me a similar screenshot that you see at your end.

image.png

If you see Purchased and no Design Linking, can you then right click on the IP Core (or on the BD, in case it is a Block Design) and selected “reset output products” and then “Regenerate output products” and then re-run synth, Implementation and generate bitstream. Then see if this time your bitstream still fails with the same error message or not?

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Explorer
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Registered: ‎09-14-2018

Re: KCU105 Example Design Write Bitstream ERROR

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Hello Anatoli,

I have attached the snap shots showing the Design_Lin status of the IP.

 Actually, I do not need Ethernet IPs. I just tried to re-generate the FPGA image from Xilinx sources. It turned out that the license is not the only issue. Constraint files do not full match the design due to

[DRC NSTD-1]Unspecified I/O Standard:  and [DRC UCIO-1]Unconstrained Logical Port: (Pin numbers).


Please see another case: KCU105 IPI Design Write Bitstream ERROR IO constraints

https://forums.xilinx.com/t5/Implementation/KCU105-IPI-Design-Write-Bitstream-ERROR-IO-constraints/m-p/1101191#M27633

Not sure how the original images were generated by Xilinx?

Thank you.

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Moderator
Moderator
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Registered: ‎06-14-2010

Re: KCU105 Example Design Write Bitstream ERROR

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Hello @arotenst ,

If you see Design_linking for your AXI 1G/2.5G Ethernet Subsystem, that is the reason for the licensing error you've shared in the original post.

Do you have a tri_mode_eth_mac IP Core license in place? Please note that you'd need a Tri-mode Ethernet Media Access Controller (TEMAC) license for this IP.

You can obtain a free Hardware Evaluation license for this IP from here: https://www.xilinx.com/products/intellectual-property/axi_ethernet.html

Here is a direct link for it: https://www.xilinx.com/member/forms/license-form.html?tab=CreateLicense&product=0451141

Once you have this license generated and installed, when you re-do report_ip_status, you should then see HW_Eval instead of Design_Linking, and if that is the case, right click on this IP and do reset and then regenerate output products for this IP first and then re-run Synthesis, Implementation and then generate Bitgen. Then see if you still seeing the same error or not.

Hope this helps.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Explorer
Explorer
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Registered: ‎09-14-2018

Re: KCU105 Example Design Write Bitstream ERROR

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Hello Anatoli,

Thank you for the explanations.

 

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