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Newbie xilinxforum
Newbie
7,244 Views
Registered: ‎06-27-2014

Viterbi Decoder 7.0 and 8.0, License failure - Required Hardware_Evaluation or Bought license for the block

Hi,

 

I am not sure if this is the right place to post it. I have been using Xilinx System Generator (not sure if this is right name to call it) on Simulink (Matlab 2011a) and window 7. I just got “Viterbi Decoder” evaluation license. I have rebooted my computer.

 

I have tried to use both “Viterbi Decoder 7.0” and “Viterbi Decoder 8.0” blocks and got following message;

 

License failure - Required Hardware_Evaluation or Bought license for the block

Error occurred during "HDL Netlist Generation".

Error occurred during "Simulation Initialization".

 

An internal error occurred in the Xilinx Blockset Library.

Please report this error to Xilinx (http://support.xilinx.com), in as much detail as possible. You may also find immediate help in the Answers Database and other online resources at http://support.xilinx.com.

Error occurred during "HDL Netlist Generation".

Error occurred during "Simulation Initialization".

 

There is a similar case in

http://forums.xilinx.com/t5/DSP-Tools/install-Viterbi-Core-license-problem/m-p/307233#M6553

 

But, his can use “Viterbi Decoder 7.0”. Mine can not.

 

Do not know how to fix this problem.

 

Thanks

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7 Replies
Xilinx Employee
Xilinx Employee
7,239 Views
Registered: ‎02-06-2013

Re: Viterbi Decoder 7.0 and 8.0, License failure - Required Hardware_Evaluation or Bought license for the block

Hi

 

We have seen issues with System generator not detecting the viterbi Decoder licenses properly.

 

What is the ISE version you are using.

 

ISE14.3 should work with viterbi Decoder 7.0

 

Also check if the license for this core is picking correctly by checking the license status in the core generator or xinfo file.

Regards,

Satish

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Newbie xilinxforum
Newbie
7,237 Views
Registered: ‎06-27-2014

Re: Viterbi Decoder 7.0 and 8.0, License failure - Required Hardware_Evaluation or Bought license for the block

Hi,

Thanks for your reply. I just installed ISE recently. But, my window tells me it is Xilinx ISE Design Suite 13.4. My “Manage Xilinx Licenses” tag shows “viterbi_v4_0”.

Any suggestion?

Thanks
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Xilinx Employee
Xilinx Employee
7,205 Views
Registered: ‎02-06-2013

Re: Viterbi Decoder 7.0 and 8.0, License failure - Required Hardware_Evaluation or Bought license for the block

Hi

 

Can you post your xinfo file and the viterbi decoder license file.

Regards,

Satish

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Give Kudos to a post which you think is helpful.
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5,454 Views
Registered: ‎05-27-2015

Re: Viterbi Decoder 7.0 and 8.0, License failure - Required Hardware_Evaluation or Bought license for the block

Hi,

 

Did you gor solution of subjected error ?

 

Please advise if any workaround is available. I am also dealing with similar error.

 

Thanks in advance !!!

 

 

Regards,

Hardik Purohit


@yenigal wrote:

Hi

 

Can you post your xinfo file and the viterbi decoder license file.


 

 

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Visitor sushma@22
Visitor
1,500 Views
Registered: ‎12-27-2017

Re: Viterbi Decoder 7.0 and 8.0, License failure - Required Hardware_Evaluation or Bought license for the block

hi...

Did you solve that problem because i m getting same problem with viterbi decoder 7.0 and 8.0 version. 

Kindly intimate me where z the problem..

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Moderator
Moderator
1,394 Views
Registered: ‎06-14-2010

Re: Viterbi Decoder 7.0 and 8.0, License failure - Required Hardware_Evaluation or Bought license for the block

Hello sushma@22,

 

Do you actually have a Hardware_Evaluation or Bought license for this IP Core?

If not, you can obtain a Hardware Evaluation license for this Viterbi Decoder Core from www.xilinx.com/getlicenses.

 

* A Hardware Evaluation license for any of the IP cores will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.

The IP cores will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.

 

If you have any questions, please let me know.

 

Kind Regards,

Anatoli

Kind Regards,
Anatoli Curran,
Xilinx Technical Support
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Visitor sushma@22
Visitor
801 Views
Registered: ‎12-27-2017

Re:

Hi

Getting problem with black box block.. Initially I wrote a vhdl code with four sub .vhd files in ISE webpack.. That code is loaded into black box, showing NAN output even black box property is modified into ISE simulator.. There is any other procedure to load all those files.. Kindly give reply this mail id koyeladasushma@gmail.com.. I am working on system generator, but just i am in a learning stage so kindly reply me as soon as possible.

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