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Registered: ‎10-31-2016

Vivado 2018.3 HDMI IP: Command failed: This design contains one or more cells for which bitstream generation is not permitted



I upgraded my Vivado from 2018.1 to 2018.3 and then update my project to the same. After this I continously get an error and coulndnot generate bit file (not generate bit). I also did what msg suggested, still it is not working.

I am getting a msg :

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted:
design_1_i/hdmi_display_path/v_hdmi_tx_ss_0/U0/v_hdmi_tx/inst (<encrypted cellview>)
If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation.


where as when I check the IP, it says that license is available:



Please let me know how can I solve this problem.


Thanking you 

Kind regards 

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1 Reply
Registered: ‎06-14-2010

Hello @msh,

The problem here is that your current netlist wasn't updated since your new HW Eval license was added and that is causing your issue, as your netlist was built at the time when you had only Design_Linking license for this IP Core.

Please have a look at the following AR:

Basically, when the IP core is generated, the license information is stored in the netlist file and it stays in the netlist file even after you change the license to something else (i.e. if you had no license first and then added a full, purchased license (or an evaluation one) afterwards - then you need to update the output products to update the netlist).

If the output products are not updated, then the old license will still be pointed to even after a valid license is installed. As such, please follow the steps given in the above Answer Record and that should help you to resolve your licensing issue, as I believe that you have added the new license file, but the netlist wasn't updated and still contains incorrect licensing info.

So, can you please right click on the IP Core and selected “reset outputs product”, then "re-generate output products" and then re-run synth, Implementation and generate bitstream. This will solve your issue then.

Hope this helps.

Kind Regards,
Anatoli Curran,
Xilinx Technical Support

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