cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
sridhargunnam
Observer
Observer
3,507 Views
Registered: ‎06-16-2017

mipi-csi2-rx example design licence error

Jump to solution

Hi,

 

I am new to Xilinx tools. I am trying to use zynq ultrascale+ to characterize camera pipeline. I am trying to setup the IMX274 to display the video to hdmi output. I got started with mipi_csi2_rx_subsystem using below document. I instantiated the IP, created output products and then tried to open the IP example project of mipi_csi2_rx_subsystem. I got the following licence error shown in the snippet. But when I checked in Xilinx licence manager, it shows that I have licence for mipi_csi2_rx_ctrl block.

 

https://www.xilinx.com/support/documentation/ip_documentation/mipi_csi2_rx_subsystem/v3_0/pg232-mipi-csi2-rx.pdf

 

Can you help mw with the below questions.

1) Do I need to buy licence?

2) Where can I find reference designs to use IMX274 on ultrascale+

 

Thanks,

Sridhar Gunnam

error.PNG
licence_managert.PNG
0 Kudos
1 Solution

Accepted Solutions
florentw
Moderator
Moderator
4,644 Views
Registered: ‎11-09-2015

Hi @sridhargunnam,

 

I confirmed that you need the following licenses (all available as Hardware Evaluation or free (TPG) licenses):

- MIPI CSI2

- VPSS

- HDMI

- MIPI DSI TX

- TPG

 

I have written AR#70308 (might be online in few days) to capture this information.

 

Note that you don't need the HDMI license to build the BD, so you can generate it and remove the HDMI IP before generating the bitstream.

 

If you are using windows OS:

  • Make sure you are using a very short path. Else you might see error with the GAMMA LUT and Demosaic IP. What I have done is to generate the BD and then save the project as with a very short name (I have used project name "X" directly under my C: drive)
  • As you are using a Hardware Evaluation license, you should see AR#70165 (also valid for the MIPI Subsystems)

If everything is clear for you on this subject, please kindly mark a response as solution to close the thread.

 

Best Regards,

 

Florent

Product Application Engineer - Video and Embedded


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

9 Replies
thakurr
Moderator
Moderator
3,485 Views
Registered: ‎09-15-2016

@sridhargunnam

 

Can you run the below command in the tcl console and make sure all the IPs are up to date:

report_ip_status

 

If IPs are not updated, run the below command in the tcl console:

upgrade_ip [get_ips]

 

Regards

Rohit

----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

 

Regards
Rohit
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
----------------------------------------------------------------------------------------------

0 Kudos
sridhargunnam
Observer
Observer
3,472 Views
Registered: ‎06-16-2017

Thanks for the reply.

 

The IP are up to date. Do you think there any other issues? 

 

One thing I observed is that when customizing the IP, I didn't see the tab for board, which is present in the figures shown in the documentation. Please find them in the attachments. 

 

I was trying to use mipi_csi2_rx with IMX274 camera sensor. I instantiated the IP in vivado, did "generate output products", then tried to open the example design project, as I am unsure of all the connections to this IP block. Do you think there is a better way to use these IP's? The mipi_csi2_rx IP documentation is not clear on how to build example design. 

 

 

report_ip_status 

-------------------------------------------------------------------------------------------------------------------------------------------------------------

IP Status Summary

1. Project IP Status
--------------------
Your project uses 12 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions.

More information on the Xilinx versioning policy is available at www.xilinx.com.

Project IP Instances
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part |
| | | | Log | | Version | | License | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_subsystem_0 | Up-to-date | No changes required | *(1) | MIPI CSI-2 Rx | 3.0 | 3.0 | Purchased | xczu9eg-ffvb1156-2-e |
| | | | | Subsystem | | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_phy_0 | Up-to-date | No changes required | *(2) | MIPI D-PHY | 4.0 | 4.0 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_r_sync_0 | Up-to-date | No changes required | *(3) | Processor System | 5.0 | 5.0 (Rev. 12) | Included | xczu9eg-ffvb1156-2-e |
| | | | | Reset | (Rev. | | | |
| | | | | | 12) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_rx_0 | Up-to-date | No changes required | *(4) | MIPI CSI-2 Rx | 1.0 | 1.0 (Rev. 6) | Purchased | xczu9eg-ffvb1156-2-e |
| | | | | Controller | (Rev. | | | |
| | | | | | 6) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0 | Up-to-date | No changes required | Change | Video Format | 1.0 | 1.0 (Rev. 8) | Included | xczu9eg-ffvb1156-2-e |
| | | | Log not | Bridge | (Rev. | | | |
| | | | available | | 8) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_phy_0_hssio_rx | Up-to-date | No changes required | *(5) | High Speed | 3.2 | 3.2 (Rev. 2) | Included | xczu9eg-ffvb1156-2-e |
| | | | | SelectIO Wizard | (Rev. | | | |
| | | | | | 2) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0_axis_converter | Up-to-date | No changes required | *(6) | AXI4-Stream Data | 1.1 | 1.1 (Rev. 13) | Included | xczu9eg-ffvb1156-2-e |
| | | | | Width Converter | (Rev. | | | |
| | | | | | 13) | | | |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| bd_639e_0_vfb_0_0_fifo | Up-to-date | No changes required | *(7) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fc_322048 | Up-to-date | No changes required | *(8) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo0 | Up-to-date | No changes required | *(9) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo1 | Up-to-date | No changes required | *(10) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
| mipi_csi2_rx_ctrl_v1_0_6_fifo2 | Up-to-date | No changes required | *(11) | FIFO Generator | 13.2 | 13.2 | Included | xczu9eg-ffvb1156-2-e |
+------------------------------------+------------+---------------------+-----------+--------------------+---------+---------------+------------+----------------------+
*(1) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_csi2_rx_subsystem_v3_0/doc/mipi_csi2_rx_subsystem_v3_0_changelog.txt
*(2) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_dphy_v4_0/doc/mipi_dphy_v4_0_changelog.txt
*(3) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/proc_sys_reset_v5_0/doc/proc_sys_reset_v5_0_changelog.txt
*(4) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/mipi_csi2_rx_ctrl_v1_0/doc/mipi_csi2_rx_ctrl_v1_0_changelog.txt
*(5) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/high_speed_selectio_wiz_v3_2/doc/high_speed_selectio_wiz_v3_2_changelog.txt
*(6) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/axis_dwidth_converter_v1_1/doc/axis_dwidth_converter_v1_1_changelog.txt
*(7) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(8) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(9) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(10) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt
*(11) c:/Xilinx/Vivado/2017.3/data/ip/xilinx/fifo_generator_v13_2/doc/fifo_generator_v13_2_changelog.txt

-------------------------------------------------------------------------------------------------------------------------------------------------------------

 

 

Below is the log for update_ip command:

 

upgrade_ip [get_ips mipi_*]
WARNING: [Coretcl 2-1042] No IP was identified for upgrade.

 

board_tab_present_in_documentation_pdf.PNG
board_tab_missing.PNG
0 Kudos
sridhargunnam
Observer
Observer
3,430 Views
Registered: ‎06-16-2017

Some extra information on the error I am getting. 

 

When I open example IP Design for MIPI_CSI2_RX_subsystem, I get following design with missing blocks. Can you help me how to proceed? 

 

Thanks, 

Sridhar

example_design_licence_error.PNG
0 Kudos
florentw
Moderator
Moderator
3,379 Views
Registered: ‎11-09-2015

Hi @sridhargunnam,

 

The MIPI CSI2 Example design is a full design which uses several xilinx IPs which requires a license:

MIPI.PNG

 

The CSI2 RX is used to connect with the sensor but then the VPSS is used for processing (and requires a license).

 

And to output the video, the DSI TX IP is used as well as the HDMI IP (and the both require a license).

 

You need (at least) the following HW evaluation licenses to generate the CSI2 RX example design:

-MIPI CSI2

- VPSS

- HDMI

- MIPI DSI TX

 

You might also require a license for the TPG but it is a free full license.

 

The first license missing in your case is the MIPI DSI but you might have other issues later if you don't have all the licenses required.

 

The documentation is not clear about which licencing are needed for the MIPI CSI2 example design. I will report this to have the documentation updated and I will write an Answer Record for this.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
florentw
Moderator
Moderator
4,645 Views
Registered: ‎11-09-2015

Hi @sridhargunnam,

 

I confirmed that you need the following licenses (all available as Hardware Evaluation or free (TPG) licenses):

- MIPI CSI2

- VPSS

- HDMI

- MIPI DSI TX

- TPG

 

I have written AR#70308 (might be online in few days) to capture this information.

 

Note that you don't need the HDMI license to build the BD, so you can generate it and remove the HDMI IP before generating the bitstream.

 

If you are using windows OS:

  • Make sure you are using a very short path. Else you might see error with the GAMMA LUT and Demosaic IP. What I have done is to generate the BD and then save the project as with a very short name (I have used project name "X" directly under my C: drive)
  • As you are using a Hardware Evaluation license, you should see AR#70165 (also valid for the MIPI Subsystems)

If everything is clear for you on this subject, please kindly mark a response as solution to close the thread.

 

Best Regards,

 

Florent

Product Application Engineer - Video and Embedded


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**

View solution in original post

sridhargunnam
Observer
Observer
3,355 Views
Registered: ‎06-16-2017

Thank you @florentw for the detailed response. 

 

 

Buying individual license as and when required may hinder our design time.

 

Is there a documentation which gives us an idea of different IP cores most used in Image processing? Do you know if there is a bundled license package that I can purchase?

 

I am a research student and funds for the license are limited. So I need to look in terms of price point as well. (Please let us know if there are any special offers for student researchers.)

 

Thanks,

Sridhar

 

 

 

0 Kudos
florentw
Moderator
Moderator
3,350 Views
Registered: ‎11-09-2015

Hi @sridhargunnam,

 

This is a different question. Could you close this thread (mark the best response a solution) and open a new thread in the DSP and Video board?

 

I will try to answer.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
andrewngo
Contributor
Contributor
2,804 Views
Registered: ‎03-23-2018

Hi,

I am trying to compile MIPI CSI-2 Development Application Example, and get several errors which lead me to this post, and help me go thru all step until generate bit file. In order to generate a bit file (witch support HDMI output), look like I need a license for HDMI IP, I manage to get Hardware Eval license from Xilinx (which will expired around next 3 months) but after update license, using report_ip_status return Design_Linking license which mean bit stream generate is prohibited.

 

My question is: do I need to buy a license for HDMI TX IP in order to generate bit file?

 

Thanks

 

0 Kudos
florentw
Moderator
Moderator
2,755 Views
Registered: ‎11-09-2015

HI @andrewngo,

 

No you can generate the example design with a HDMI example design.

 

Please create a new topic in the Installation and Licensing board to ask why the evaluation license is not working.

 

Note: I am closing this topic as it was already solved.

 

Regards,


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos