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Observer cetic.ecs.fpga
Observer
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Registered: ‎05-23-2019

DPU TRD 3.0 for ZCU104

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I am trying to retarget  DPU TRD to the ZCU104 board from zcu102-dpu-trd-2019-1-190809. I have built the Vivado project thanks to zcu104.tcl provided in "DPU TRD for ZCU104 ?" post.  After implementation, many timing errors are reported :

Capture1.PNGCapture2.PNG

It seems that to many resources are required for the design. Can you tell me how to reduce resources according to the DPU options? May be only one DPU core instead of two?

Then I intend to generate the Linux platform with PetaLinux and build the application with xilinx_dnndk_v3.1.

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Observer cetic.ecs.fpga
Observer
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Registered: ‎05-23-2019

Re: DPU TRD 3.0 for ZCU104

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I can get Resnet50 working on ZCU104 now, following the steps hereunder:

    1 - I started from xilinx_dnndk_v3.1_190809 Resnet_50 Caffe model, by running decent with a set of 250 images downloaded from imagenet, and then dnnc for ZCU104 with the.dcf file generated on the vivado DPU project. 1 DPu core is instantiated
DNNDK_V3.1 is installed on a "Ubuntu 16.04.6" host

    2 - I downloaded "zcu102-dpu-trd-2019-1-190809" and the TCL script from "

DPU TRD for ZCU104 ? " post to generate my own zcu104_dpu-trd Vivado project.
    - There are minor errors in the ZCU104.tcl than can be easily corrected.
    - Many timing errors were reported in the implemented design, with Vivado 2018.3. In the "utilization diagram" I noticed that the % of resources was high. There are less logic resources in ZCU104 MPSoc than in  ZCU102. So I implemented only one DPU core (in DPU configuration) and got good results.

    3 - Petalinux project : petalinux 209.1 and SDK2019.1
        I followed the DPU integration tutorial :
            - I created the project from the xilinx-dpu-trd-zcu102-v2019.1.bsp
            - change the "STG Setting" to zcu104-revc
        Then in the end, the BOOT.BIN and image.ub were generated, DPU core included.
 
    4 - SDK : The end of the "DPU Integration Tutorial" explains how to compile the application and the CNN, taking into account the sysroot.

 

Then resnet50 can process a set 500 VGA images in about 20secondes (DPU being in debug mode) on the ZCU104 board.

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Observer apierp
Observer
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Registered: ‎04-15-2019

Re: DPU TRD 3.0 for ZCU104

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I am curious to hear your updates. As far as I know, the TRD is specfically targeted for the 102 board - which has some major differences with the 104. So this task probably isnt so straightforward.
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Observer cetic.ecs.fpga
Observer
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Registered: ‎05-23-2019

Re: DPU TRD 3.0 for ZCU104

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Hello,

You can look at this post : "DPU TRD for ZCU104 ?". The vivado project for ZCU104 board can be generated from the zcu102-dpu-trd-2019-1-190809 and the tcl script provided in the post.

I was not expecting to have the problems mentionned in this post with the latest version of DPU. I am using vivado 2018.3, which seems to be the source of the timing errors. I don't understand why. As indicated in "DPU TRD for ZCU104 ?", the only solution is unfortunatly to keep vivado 2018.2 and zcu102-dpu-trd-2018-2-190531...

For now, I will try to implement the DPU with only one core, instead of two

 

 

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Observer cetic.ecs.fpga
Observer
288 Views
Registered: ‎05-23-2019

Re: DPU TRD 3.0 for ZCU104

Jump to solution

I can get Resnet50 working on ZCU104 now, following the steps hereunder:

    1 - I started from xilinx_dnndk_v3.1_190809 Resnet_50 Caffe model, by running decent with a set of 250 images downloaded from imagenet, and then dnnc for ZCU104 with the.dcf file generated on the vivado DPU project. 1 DPu core is instantiated
DNNDK_V3.1 is installed on a "Ubuntu 16.04.6" host

    2 - I downloaded "zcu102-dpu-trd-2019-1-190809" and the TCL script from "

DPU TRD for ZCU104 ? " post to generate my own zcu104_dpu-trd Vivado project.
    - There are minor errors in the ZCU104.tcl than can be easily corrected.
    - Many timing errors were reported in the implemented design, with Vivado 2018.3. In the "utilization diagram" I noticed that the % of resources was high. There are less logic resources in ZCU104 MPSoc than in  ZCU102. So I implemented only one DPU core (in DPU configuration) and got good results.

    3 - Petalinux project : petalinux 209.1 and SDK2019.1
        I followed the DPU integration tutorial :
            - I created the project from the xilinx-dpu-trd-zcu102-v2019.1.bsp
            - change the "STG Setting" to zcu104-revc
        Then in the end, the BOOT.BIN and image.ub were generated, DPU core included.
 
    4 - SDK : The end of the "DPU Integration Tutorial" explains how to compile the application and the CNN, taking into account the sysroot.

 

Then resnet50 can process a set 500 VGA images in about 20secondes (DPU being in debug mode) on the ZCU104 board.

Adventurer
Adventurer
225 Views
Registered: ‎06-09-2015

Re: DPU TRD 3.0 for ZCU104

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For the DPU TRD for ZCU104 with DPU 3.0/DNNDK 3.1 with VIVADO 2018.3 or 2019.1, the timing issue can be solved using “set_param place.runPartPlacer 0” in the Tcl Console before the implementation. This thread have discussion on it: zcu104 DPU TRD with vivado 2018.2 and 2019.1

Regards,
krishna@logictronix.com