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Participant sauvagya30
Participant
579 Views
Registered: ‎08-26-2019

DPU TRD for Zedboard

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I am having makefile for ZCU102.

how can i modify the make file of ZCU102, to generate RESNET 50 FOR ZEDBOARD

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Xilinx Employee
Xilinx Employee
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Registered: ‎11-28-2007

回复: DPU TRD for Zedboard

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Did you rebuild the SDK?

Pls. try the following steps.

cd $TRD_HOME/apu/dpu_petalinux_bsp/your_petlinux_project
petalinux-build --sdk
cd $TRD_HOME/apu/dpu_petalinux_bsp/your_petlinux_project/images/linux
./sdk.sh -d ./sdk -y

unset LD_LIBRARY_PATH

. $TRD_HOME/apu/dpu_petalinux_bsp/your_petlinux_project/images/linux/sdk/environment-setup-cortexa9t2hf-neon-xilinx-linux-gnueabi

## Build the resnet50 example
cd $TRD_HOME/apu/apps/resnet50
make

 

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Participant bokyung86
Participant
518 Views
Registered: ‎03-27-2013

Re: DPU TRD for Zedboard

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See my Makefile.

You need to change the path to match your computer.

 

----------------------------------------------------------------------------------------

PROJECT = resnet50
SYSROOT = /home/bkkim/workpsace/EFIS/petalinux/images/linux/sdk/sysroots/x86_64-petalinux-linux


CXX := arm-linux-gnueabihf-g++
CC := arm-linux-gnueabihf-gcc
OBJ := main.o


# linking libraries of OpenCV
LDFLAGS += $(shell PKG_CONFIG_PATH=${SYSROOT}/usr/lib/pkgconfig pkg-config --libs opencv)
# linking libraries of DNNDK
LDFLAGS += -lhineon -ln2cube -ldputils -lpthread

CUR_DIR = $(shell pwd)
src=$(CUR_DIR)/src
BUILD = $(CUR_DIR)/build
MODEL = $(CUR_DIR)/model
VPATH = $(SRC)

CFLAGS := -O2 -Wall -Wpointer-arith -std=c++11 -ffast-math -mcpu=cortex-a9 -mfloat-abi=hard -mfpu=neon
CFLAGS += --sysroot=${SYSROOT}

MODEL = $(CUR_DIR)/model/dpu_resnet50_0.elf

.PHONY: all clean

all: $(BUILD) $(PROJECT)

$(PROJECT) : $(OBJ)
$(CXX) $(CFLAGS) $(addprefix $(BUILD)/, $^) $(MODEL) -o $@ $(LDFLAGS)

%.o : %.cc
$(CXX) -c $(CFLAGS) $< -o $(BUILD)/$@

clean:
$(RM) -rf $(BUILD)/*.o $(BUILD)
$(RM) $(PROJECT)

$(BUILD) :
-mkdir -p $@

----------------------------------------------------------------------------------------

Best regards,

Xilinx Employee
Xilinx Employee
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Registered: ‎03-27-2013

回复: DPU TRD for Zedboard

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And if you create the petalinux image following the steps in https://github.com/Xilinx/Edge-AI-Platform-Tutorials/tree/master/docs/DPU-Integration

You can also try the SDK building flow inside: Chapter "Build Machine Learning Applications Using Xilinx SDK"

Best Regards,
Jason
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Participant sauvagya30
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487 Views
Registered: ‎08-26-2019

Re: DPU TRD for Zedboard

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Thanks for ur reply.

but i am getting the following error:

sahoo@sahoo-Veriton-M4630G:~/ZED_chek_oct18/image_creation_resnet50/resnet50$ make
aarch64-linux-gnu-g++ -c -O2 -Wall -Wpointer-arith -std=c++11 -ffast-math -mcpu=cortex-a9 -mfloat-abi=hard -mfpu=neon --sysroot=/home/sahoo/ZED_chek_oct18/image_creation_resnet50/sdk/sysroots/aarch64-xilinx-linux /home/sahoo/ZED_chek_oct18/image_creation_resnet50/resnet50/src/main.cc -o /home/sahoo/ZED_chek_oct18/image_creation_resnet50/resnet50/build/main.o
aarch64-linux-gnu-g++: error: unrecognized command line option ‘-mfloat-abi=hard’
aarch64-linux-gnu-g++: error: unrecognized command line option ‘-mfpu=neon’
Makefile:80: recipe for target 'main.o' failed
make: *** [main.o] Error 1

i am attaching my original makefile also

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Participant bokyung86
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Registered: ‎03-27-2013

Re: DPU TRD for Zedboard

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What is your test environment?

If you are using Zedboard,
Cross compilers should use 'arm-linux-gnueabihf-'.

aarch64-linux-gnu- is a compiler for MPSoc.

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Participant sauvagya30
Participant
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Registered: ‎08-26-2019

Re: DPU TRD for Zedboard

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I AM USING ZEDBOARD

MY ORIGINAL MAKE FILE IS LIKE THIS:

 

PROJECT = resnet50
SYSROOT = /home/sahoo/ZED_chek_oct18/image_creation_resnet50/sdk/sysroots/aarch64-xilinx-linux

CXX := aarch64-linux-gnu-g++
CC := aarch64-linux-gnu-gcc
OBJ := main.o

# linking libraries of OpenCV
LDFLAGS += $(shell PKG_CONFIG_PATH=${SYSROOT}/usr/lib/pkgconfig pkg-config --libs opencv)
# linking libraries of DNNDK
LDFLAGS += -lhineon -ln2cube -ldputils -lpthread

CUR_DIR = $(shell pwd)
src=$(CUR_DIR)/src
BUILD = $(CUR_DIR)/build
MODEL = $(CUR_DIR)/model
VPATH = $(SRC)

CFLAGS := -O2 -Wall -Wpointer-arith -std=c++11 -ffast-math -mcpu=cortex-a53
CFLAGS += --sysroot=${SYSROOT}

MODEL = $(CUR_DIR)/model/dpu_resnet50_0.elf

.PHONY: all clean

all: $(BUILD) $(PROJECT)

$(PROJECT) : $(OBJ)
$(CXX) $(CFLAGS) $(addprefix $(BUILD)/, $^) $(MODEL) -o $(BUILD)/$@ $(LDFLAGS)

%.o : %.cc
$(CXX) -c $(CFLAGS) $< -o $(BUILD)/$@

clean:
$(RM) -rf $(BUILD)

$(BUILD) :
-mkdir -p $@

 

AFTER CREATING  IMAGE FOE RESNET 50, WHEN I TYPE ./RESNET50 IN ZEDBOARD LINUX TERMINAL

IT REPLY: EXECUTION FORMAT ERROR

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Participant bokyung86
Participant
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Registered: ‎03-27-2013

Re: DPU TRD for Zedboard

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The path of SYSROOT is not valid.
The compiler was incorrectly specified.
The Make file you use is for ZynqMP.

Edit the entry below by referring to the file I showed.
=> SYSROOT, CFLAGS, CXX, CC

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Participant sauvagya30
Participant
454 Views
Registered: ‎08-26-2019

Re: DPU TRD for Zedboard

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can u please tell me how to get this "Cross compilers should use 'arm-linux-gnueabihf-'"

after runnin sh sdk.sh (this sdk.sh i have collected from ZCU102), inside sysroot the folders are : "aarch64-xilinx-linux" and "x86_64-petalinux-linux".

from where i can get the ross compilers should use 'arm-linux-gnueabihf-, or sdk.sh file is different for zedboard.

can u please tell me from where i can get sdk.sh for zedboard to create image file for resnet 50.

 

Best Regards and Thanks

 

 

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Participant sauvagya30
Participant
378 Views
Registered: ‎08-26-2019

Re: DPU TRD for Zedboard

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as u told , i download cross compiler Cross compilers should use 'arm-linux-gnueabih-'., but now the error is

Makefile:75: recipe for target 'resnet50' failed

 

can u please suggest, my new makefile is like this (ZEDBOARD)

PROJECT = resnet50
SYSROOT = /home/sahoo/ZED_chek_oct18/image_creation_resnet50/sdk/sysroots/cortexa9hf-neon-xilinx-linux-gnueabi

CXX := arm-xilinx-linux-gnueabi-g++
CC := arm-xilinx-linux-gnueabi-gcc
OBJ := main.o

# linking libraries of OpenCV
LDFLAGS += $(shell PKG_CONFIG_PATH=${SYSROOT}/usr/lib/pkgconfig pkg-config --libs opencv)
# linking libraries of DNNDK
LDFLAGS += -lhineon -ln2cube -ldputils -lpthread

CUR_DIR = $(shell pwd)
src=$(CUR_DIR)/src
BUILD = $(CUR_DIR)/build
MODEL = $(CUR_DIR)/model
VPATH = $(SRC)

CFLAGS := -O2 -Wall -Wpointer-arith -std=c++11 -ffast-math -mcpu=cortex-a9 -mfloat-abi=hard
CFLAGS += --sysroot=${SYSROOT}

MODEL = $(CUR_DIR)/model/dpu_resnet50_0.elf

.PHONY: all clean

all: $(BUILD) $(PROJECT)

$(PROJECT) : $(OBJ)
$(CXX) $(CFLAGS) $(addprefix $(BUILD)/, $^) $(MODEL) -o $(BUILD)/$@ $(LDFLAGS)

%.o : %.cc
$(CXX) -c $(CFLAGS) $< -o $(BUILD)/$@

clean:
$(RM) -rf $(BUILD)

$(BUILD) :
-mkdir -p $@

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Participant sauvagya30
Participant
357 Views
Registered: ‎08-26-2019

回复: DPU TRD for Zedboard

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after following ur steps for my zedboard i am getting following error:

fatal error: dnndk/dnndk.h: No such file or directory
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Xilinx Employee
Xilinx Employee
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Registered: ‎11-28-2007

回复: DPU TRD for Zedboard

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Did you rebuild the SDK?

Pls. try the following steps.

cd $TRD_HOME/apu/dpu_petalinux_bsp/your_petlinux_project
petalinux-build --sdk
cd $TRD_HOME/apu/dpu_petalinux_bsp/your_petlinux_project/images/linux
./sdk.sh -d ./sdk -y

unset LD_LIBRARY_PATH

. $TRD_HOME/apu/dpu_petalinux_bsp/your_petlinux_project/images/linux/sdk/environment-setup-cortexa9t2hf-neon-xilinx-linux-gnueabi

## Build the resnet50 example
cd $TRD_HOME/apu/apps/resnet50
make

 

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Participant sauvagya30
Participant
276 Views
Registered: ‎08-26-2019

回复: DPU TRD for Zedboard

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Thanks  

root@zed_deephi:/media/card/build# ./resnet50

####################################################
Warning:
The DPU in this TRD can only work 8 hours each time!
Please consult Sales for more details about this!
####################################################

Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e1e51 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e1ef1 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e1f91 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2031 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e20d1 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2175 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2215 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e22b5 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2359 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e23f9 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2499 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e253d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e25dd FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e267d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e271d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e27c1 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2861 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2901 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e29a5 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2a45 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2ae5 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2b89 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2c29 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2cc9 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2d6d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2e0d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2ead FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2f4d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e2ff1 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3091 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3131 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e31d5 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3275 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3315 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e33b9 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3459 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e34f9 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e359d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e363d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e36dd FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3781 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3821 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e38c1 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3965 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3a05 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3aa5 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3b45 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3be9 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3c89 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3d29 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3dcd FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3e6d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3f0d FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e3fb1 FSR 0x011
Alignment trap: resnet50 (1464) PC=0xb6c67b36 Instr=0xe9d60102 Address=0xb48e4001 FSR 0x011
total image : 10
[DPU][1468][PID 1468][taskID 4]Core 0 Run timeout,failed to get finish interrupt!
[DPU][1468][DPU debug info]
level = 9
[DPU][1468]Core 0 schedule counter: 1
[DPU][1468]Core 0 interrupt counter: 0
[DPU][1468][DPU Registers]
[DPU][1468]VER : 0x09298cfb
[DPU][1468]RST : 0x000000ff
[DPU][1468]ISR : 0x00000000
[DPU][1468]IMR : 0x00000000
[DPU][1468]IRSR : 0x00000000
[DPU][1468]ICR : 0x00000000
[DPU][1468]
[DPU][1468]DPU Core : 0
[DPU][1468]HP_CTL : 0x07070f0f
[DPU][1468]ADDR_IO : 0x00000000
[DPU][1468]ADDR_WEIGHT : 0x00000000
[DPU][1468]ADDR_CODE : 0x00018048
[DPU][1468]ADDR_PROF : 0x00000000
[DPU][1468]PROF_VALUE : 0x00000000
[DPU][1468]PROF_NUM : 0x00000000
[DPU][1468]PROF_EN : 0x00000000
[DPU][1468]START : 0x00000001
[DPU][1468]COM_ADDR_L0 : 0x18300000
[DPU][1468]COM_ADDR_H0 : 0x00000000
[DPU][1468]COM_ADDR_L1 : 0x1a500000
[DPU][1468]COM_ADDR_H1 : 0x00000000
[DPU][1468]COM_ADDR_L2 : 0x18048000
[DPU][1468]COM_ADDR_H2 : 0x00000000
[DPU][1468]COM_ADDR_L3 : 0x00000000
[DPU][1468]COM_ADDR_H3 : 0x00000000
[DPU][1468]COM_ADDR_L4 : 0x00000000
[DPU][1468]COM_ADDR_H4 : 0x00000000
[DPU][1468]COM_ADDR_L5 : 0x00000000
[DPU][1468]COM_ADDR_H5 : 0x00000000
[DPU][1468]COM_ADDR_L6 : 0x00000000
[DPU][1468]COM_ADDR_H6 : 0x00000000
[DPU][1468]COM_ADDR_L7 : 0x00000000
[DPU][1468]COM_ADDR_H7 : 0x00000000
[DPU][1468]
[DNNDK] DPU timeout while execute DPU Task [resnet50_0-4] of Node [conv1]

 

can u please address this

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Xilinx Employee
Xilinx Employee
227 Views
Registered: ‎11-28-2007

回复: DPU TRD for Zedboard

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Do you see the DPU interrupt? You can have a look by using this command: cat /proc/interrupts

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Participant sauvagya30
Participant
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Registered: ‎08-26-2019

回复: DPU TRD for Zedboard

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After running this command

root@zed_deephi:/media/card/face_detection/model# cat /proc/interrupts

 

CPU0 CPU1
16: 1 0 GIC-0 27 Edge gt
17: 0 0 GIC-0 43 Level ttc_clockevent
18: 2316 4559 GIC-0 29 Edge twd
19: 0 0 GIC-0 37 Level arm-pmu
20: 0 0 GIC-0 38 Level arm-pmu
21: 43 0 GIC-0 39 Level f8007100.adc
24: 0 0 GIC-0 35 Level f800c000.ocmc
25: 266 0 GIC-0 82 Level xuartps
26: 8 0 GIC-0 51 Level e000d000.spi
27: 0 0 GIC-0 54 Level eth0
28: 3753 0 GIC-0 56 Level mmc0
29: 0 0 GIC-0 45 Level f8003000.dmac
30: 0 0 GIC-0 46 Level f8003000.dmac
31: 0 0 GIC-0 47 Level f8003000.dmac
32: 0 0 GIC-0 48 Level f8003000.dmac
33: 0 0 GIC-0 49 Level f8003000.dmac
34: 0 0 GIC-0 72 Level f8003000.dmac
35: 0 0 GIC-0 73 Level f8003000.dmac
36: 0 0 GIC-0 74 Level f8003000.dmac
37: 0 0 GIC-0 75 Level f8003000.dmac
38: 0 0 GIC-0 40 Level f8007000.devcfg
44: 0 0 GIC-0 53 Level e0002000.usb
45: 0 0 GIC-0 41 Edge f8005000.watchdog
46: 94 0 GIC-0 90 Level 41600000.i2c
47: 0 0 GIC-0 91 Edge 43c20000.dma
48: 0 0 GIC-0 61 Edge dpu_isr
IPI1: 0 0 Timer broadcast interrupts
IPI2: 1659 2272 Rescheduling interrupts
IPI3: 2 2 Function call interrupts
IPI4: 0 0 CPU stop interrupts
IPI5: 0 0 IRQ work interrupts
IPI6: 0 0 completion interrupts

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