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Ankush
Visitor
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Registered: ‎10-27-2020

48bit PL MIG DDR4 using 64bit PL DDR4 Issues

Dear Forum,

I am looking for a design that consists of PS and 48bit PL DDR4 IP.  This DDR4 is shared between the ARM processor and PL logic.

Because of limited pin on the device I am using and throughput required 32bit or 64bit DDR is not suitable for me.

The MIG DDR4 does not support 48 bit width when AXI is enabled.

 

So I came up with the workaround, I have instantiated 64 bit DDR in block design and removed the upper 16 dq signal and respective dqs and dbi signal connection in the top-level wrapper. 

I have made the pin assignment and the synthesized the design. Synthesis was complete but implementation is failing with the following errors

[DRC MDRV-1] Multiple Driver Nets: Net <const0> has multiple drivers: GND/G, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[10].u_ddr_iob_byte/genBuf[9].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[9].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[8].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[6].genBuf.IO_BUFDS/OBUFTDS/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[5].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[4].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[3].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[2].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[11].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[10].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[9].u_ddr_iob_byte/genBuf[0].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[10].u_ddr_iob_byte/genBuf[8].genblk1_1.IOBUF/OBUFT_INST/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[10].u_ddr_iob_byte/genBuf[6].genBuf.IO_BUFDS/OBUFTDS/O, design_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr_iob/genByte[10].u_ddr_iob_byte/genBuf[5].genblk1_1.IOBUF/OBUFT_INST/O... and (the first 15 of 23 listed).

This error is pointing to a NET inside the MIG DDR4 IP which are read-only files so I can't do any experiment there.

 

1. Is my approach for the design correct?

2. If yes, how can I resolve the above error in the implementation phase?

3. Is there any other way to use 48 bit DDR4 IP with AXI support?

 

the following are the block diagram and modified top-level wrapper.

ddr4_ps_bd.JPG

//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2018.2 (lin64) Build 2258646 Thu Jun 14 20:02:38 MDT 2018
//Date : Wed Oct 28 18:40:30 2020
//Host : blackperl running 64-bit Red Hat Enterprise Linux Server release 6.9 (Santiago)
//Command : generate_target design_1_wrapper.bd
//Design : design_1_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module design_1_wrapper
(ddr4_rtl_0_act_n,
ddr4_rtl_0_adr,
ddr4_rtl_0_ba,
ddr4_rtl_0_bg,
ddr4_rtl_0_ck_c,
ddr4_rtl_0_ck_t,
ddr4_rtl_0_cke,
ddr4_rtl_0_cs_n,
ddr4_rtl_0_dm_n,
ddr4_rtl_0_dq,
ddr4_rtl_0_dqs_c,
ddr4_rtl_0_dqs_t,
ddr4_rtl_0_odt,
ddr4_rtl_0_reset_n,
diff_clock_rtl_0_clk_n,
diff_clock_rtl_0_clk_p,
reset_rtl_0);
output ddr4_rtl_0_act_n;
output [16:0]ddr4_rtl_0_adr;
output [1:0]ddr4_rtl_0_ba;
output [1:0]ddr4_rtl_0_bg;
output [0:0]ddr4_rtl_0_ck_c;
output [0:0]ddr4_rtl_0_ck_t;
output [0:0]ddr4_rtl_0_cke;
output [0:0]ddr4_rtl_0_cs_n;
inout [5:0] ddr4_rtl_0_dm_n; //changed from [7:0] to [5:0] to support 48bit
inout [47:0]ddr4_rtl_0_dq; //changed from [63:0] to [47:0] to support 48bit
inout [5:0] ddr4_rtl_0_dqs_c;//changed from [7:0] to [5:0] to support 48bit
inout [5:0] ddr4_rtl_0_dqs_t;//changed from [7:0] to [5:0] to support 48bit
output [0:0]ddr4_rtl_0_odt;
output ddr4_rtl_0_reset_n;
input diff_clock_rtl_0_clk_n;
input diff_clock_rtl_0_clk_p;
input reset_rtl_0;

wire ddr4_rtl_0_act_n;
wire [16:0]ddr4_rtl_0_adr;
wire [1:0]ddr4_rtl_0_ba;
wire [1:0]ddr4_rtl_0_bg;
wire [0:0]ddr4_rtl_0_ck_c;
wire [0:0]ddr4_rtl_0_ck_t;
wire [0:0]ddr4_rtl_0_cke;
wire [0:0]ddr4_rtl_0_cs_n;
wire [5:0]ddr4_rtl_0_dm_n; //changed from [7:0] to [5:0] to support 48bit
wire [47:0]ddr4_rtl_0_dq; //changed from [63:0] to [47:0] to support 48bit
wire [5:0]ddr4_rtl_0_dqs_c;//changed from [7:0] to [5:0] to support 48bit
wire [5:0]ddr4_rtl_0_dqs_t;//changed from [7:0] to [5:0] to support 48bit
wire [0:0]ddr4_rtl_0_odt;
wire ddr4_rtl_0_reset_n;
wire diff_clock_rtl_0_clk_n;
wire diff_clock_rtl_0_clk_p;
wire reset_rtl_0;

design_1 design_1_i
(.ddr4_rtl_0_act_n(ddr4_rtl_0_act_n),
.ddr4_rtl_0_adr(ddr4_rtl_0_adr),
.ddr4_rtl_0_ba(ddr4_rtl_0_ba),
.ddr4_rtl_0_bg(ddr4_rtl_0_bg),
.ddr4_rtl_0_ck_c(ddr4_rtl_0_ck_c),
.ddr4_rtl_0_ck_t(ddr4_rtl_0_ck_t),
.ddr4_rtl_0_cke(ddr4_rtl_0_cke),
.ddr4_rtl_0_cs_n(ddr4_rtl_0_cs_n),
.ddr4_rtl_0_dm_n(ddr4_rtl_0_dm_n),
.ddr4_rtl_0_dq(ddr4_rtl_0_dq),
.ddr4_rtl_0_dqs_c(ddr4_rtl_0_dqs_c),
.ddr4_rtl_0_dqs_t(ddr4_rtl_0_dqs_t),
.ddr4_rtl_0_odt(ddr4_rtl_0_odt),
.ddr4_rtl_0_reset_n(ddr4_rtl_0_reset_n),
.diff_clock_rtl_0_clk_n(diff_clock_rtl_0_clk_n),
.diff_clock_rtl_0_clk_p(diff_clock_rtl_0_clk_p),
.reset_rtl_0(reset_rtl_0));
endmodule

Waiting for your valuable response...

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rpr
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Registered: ‎11-09-2017

Hi

MIG AXI supports with 64bit, however 48bit width is not supported.

Regards
Pratap

Please mark the Answer as "Accept as solution" if information provided is helpful.

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Ankush
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Registered: ‎10-27-2020

Hi Pratap

Thank you for responding.

Because of the limited no of pins on FPGA in my application and throughput required I can't use 64bit or 32bit MIG DDR4 IP.

I understand that 48bit DDR is not supported by MIG, That's why I am trying to find a workaround to use 48bit.

How can resolves the error in the workaround design explained in the previous message?

Is there another workaround to use 48bit DDR with AXI support?

Regards

Ankush Chavhan