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simple.wang
Visitor
Visitor
7,907 Views
Registered: ‎08-26-2014

A problem about "after sys_rst " in the DDR3 board test

ddr3 sim pass,but  meet some problem in board test,as fellows:

1.sys_clk ,ref_clk use single_ended clk

2.mmcm_lock changed from "0" to "1"after sys_rst,but ddr3 interface cs_n,ras_n,cas_n,addr always "1",not changed, why?

 

I hope somebody can help me.

Thanks very much.

Simple

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yenigal
Xilinx Employee
Xilinx Employee
7,902 Views
Registered: ‎02-06-2013

Hi

 

Which device are you using?

 

Do you see this behaviour with example design or your own design.

 

What is the difference between simulation and HW design

 

Only rst and lock signals will hold the controller is reset state,do you see any glitches on these signals and how are you monitering the ddr3 interface signals.

 

Attach your mig.prj,ucf and captures showing the issue to look into them and give further suggestions.

Regards,

Satish

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simple.wang
Visitor
Visitor
7,895 Views
Registered: ‎08-26-2014

Hi Satish,

1.device :vc7v2000tflg1925-1,soft vivado 14.3
2.use ip example design
3.monitering the ddr3 interface signals in chipscope
only sys_clk ,and ref_clk location changed,no same with ip gen.
VREF ,VRP,VRN check ok
axi interface will cause the problem?or clk jitter?but mmcm lock.

Thanks very much.
Simple
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vsrunga
Xilinx Employee
Xilinx Employee
7,884 Views
Registered: ‎07-11-2011

Hi,

 

sys_clk ,and ref_clk location changed,no same with ip gen.

--Did you validate your syslock location using MIG verufy ucf utiliity and noticed any error?

--Did you see any critical warnings in implementation?

--DDR3 reset_n, ODT  signals are  connected properly?

--Where you able to see DDR3 CK_p/n, DQS toggling ?

 

Go through MIG 7 series hardware debug guide and cross check all the rules were followed and do step by step debug analysis

http://www.xilinx.com/support/answers/43879.html

 

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