12-02-2014 06:40 PM
ddr3 sim pass,but meet some problem in board test,as fellows:
1.sys_clk ,ref_clk use single_ended clk
2.mmcm_lock changed from "0" to "1"after sys_rst,but ddr3 interface cs_n,ras_n,cas_n,addr always "1",not changed, why?
I hope somebody can help me.
Thanks very much.
12-02-2014 06:52 PM
Which device are you using?
Do you see this behaviour with example design or your own design.
What is the difference between simulation and HW design
Only rst and lock signals will hold the controller is reset state,do you see any glitches on these signals and how are you monitering the ddr3 interface signals.
Attach your mig.prj,ucf and captures showing the issue to look into them and give further suggestions.
12-02-2014 07:09 PM
12-02-2014 07:52 PM
sys_clk ,and ref_clk location changed,no same with ip gen.
--Did you validate your syslock location using MIG verufy ucf utiliity and noticed any error?
--Did you see any critical warnings in implementation?
--DDR3 reset_n, ODT signals are connected properly?
--Where you able to see DDR3 CK_p/n, DQS toggling ?
Go through MIG 7 series hardware debug guide and cross check all the rules were followed and do step by step debug analysis