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Registered: ‎09-19-2018

A7 MIG4.2 custom 72b DDR3 calib_complete but incoherent, got compare_error

Hello,

I'm currently testing a memory design on a custom board with the following specs:

Artix xc7a200t-fbg676/-2
MIG 4.2
72b width (no ECC)
5x MT41K128M16XX-15E, flyby
sys_clk 156.25MHz ext. LVDS
ref_clk 200MHz from int. PLL
Memory clock 312.5MHz (2:1)
1.35V

I implemented the example design w. debug logic and am currently checking the results. The design is timing clean (except some VIO pathes) and constrained.
At first glance, it seems that init_calib_complete is 1, so far so good.

However, tg_compare_error is also 1. What puzzles me is that on closer examination, some of the calibration stages seem to be in an inconsistent state. There don't seem to be any errors, but some stages have their '_start' signal as 0, but '_done' as 1? It seems to me that (PRBS) Read Leveling did not run at all, so the process got stuck somewhere in between. Why is init_calib_complete  1 then?

 

grafik.png

I'll attach the full ILA file as well as relevant MIG setup files (will try in a follow up post, keep getting errors ' content type (application/octet-stream) does not match its file extension and has been removed.').

Not sure what I'll try next (no DDR expert unfortunately), and the MIG debug seems to provide guidance just in the case of any '_err'=1 situations, which don't seem to apply here (apart from the compare mismatch).

Side question: Is using an internal clock for sys_clk ("No buffer") for testing acceptable or considered bad practice?

Thanks for your help.

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Registered: ‎09-19-2018

Re: A7 MIG4.2 custom 72b 1.35V 312.5MHz calib_complete but incoherent, got compare_error

Trying to attach the files as ZIP to work around the forum 'content type' error

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Registered: ‎01-09-2019

Re: A7 MIG4.2 custom 72b 1.35V 312.5MHz calib_complete but incoherent, got compare_error

Hello @fmueck 

Have you been able to work through the debugging guide here: https://www.xilinx.com/support/answers/43879.html ?

On page 26 starts the information for debugging data error failures.  Have you been able to run both a test with continuous writes then reads of Linear Addressing, PRBS data and another with Linear data, PRBS Addressing?  That should show a full sweep of the memory region and show what kind of issues you may be having in your design, such as an issue in the addressing path or on the DQ bus.

Regarding your configuration, there is not really a way to have a 72 bit wide interface without ECC that I know of so I don't believe that is quite correct.

Regarding clocking, the MIS requires an extrnal reference clock which can be found described in the Clocking Architecture section of UG586 on page 120: https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v4_2/ug586_7Series_MIS.pdf

 

Thanks,
Caleb
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Re: A7 MIG4.2 custom 72b 1.35V 312.5MHz calib_complete but incoherent, got compare_error

Hello @calebd , thanks for getting back to me.

In the meantime, I once again did a critical schematic review and found out that in fact, the memory clock output of the IP core had its P and N legs swapped on the board. Unfortunately that's fully contained within inner layers, so a HW fix is impossible. Reading on further, I learned that the DDR commands are sampled on the rising edge and pretty much everything else is aligned to that as well, so no wonder strange things happened.

What I did try though is to manually swap the data input pins (tied to GND/VCC) on the clock output ODDR inside the IP core, to reverse the polarity that way. Apparently, it's a succes; I do not get data compare errors any more

I still don't fully understand the state of all the calibration stages, the following stages did not run (_start, _done = 0):
ocal_center
prbs_rdlvl

These stages are _done, tough _start is 0:
oclkdelay_calib_done
rdlvl (_done =x3, _start=x1)

Just wondering, is that normal?

Regarding the 72b IF, the wizard let me configure that just fine and the example design was generated accordingly. Here are some snippets from example.top:

 

-- Start of User Design wrapper top component

   component mig_7series_0
      port(
         ddr3_dq    : inout std_logic_vector(71 downto 0);
         ddr3_dqs_p : inout std_logic_vector(8 downto 0);
         ddr3_dqs_n : inout std_logic_vector(8 downto 0);

         ddr3_addr           : out std_logic_vector(13 downto 0);
         ddr3_ba             : out std_logic_vector(2 downto 0);
         ddr3_ras_n          : out std_logic;
         ddr3_cas_n          : out std_logic;
         ddr3_we_n           : out std_logic;
         ddr3_reset_n        : out std_logic;
         ddr3_ck_p           : out std_logic_vector(0 downto 0);
         ddr3_ck_n           : out std_logic_vector(0 downto 0);
         ddr3_cke            : out std_logic_vector(0 downto 0);
         ddr3_cs_n           : out std_logic_vector(0 downto 0);
         ddr3_odt            : out std_logic_vector(0 downto 0);
         app_addr            : in  std_logic_vector(27 downto 0);
         app_cmd             : in  std_logic_vector(2 downto 0);
         app_en              : in  std_logic;
         app_wdf_data        : in  std_logic_vector(287 downto 0);

 

 

Regards,
fmueck

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