cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
973 Views
Registered: ‎02-13-2019

ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

Hi guys, in this post, https://forums.xilinx.com/t5/Memory-Interfaces-and-NoC/I-O-pins-of-one-HP-bank-working-at-different-voltage-levels/m-p/1072982#M16245  It has been discused a matter I've been having in order to be able to use a DDR3 SDRAM. Almost at the end of the post I say that in order to use the DDR3 that is used with the xilinx MIG, I need to relocate some ADC signals in order to get empty an HP bank needed for the memory.

a bit  better explained: 

I just have available bank 34 for the DDR3; the banks  (banks to 1.8V) 33 and 32 are full and partially  full, respectivelly (the partially full means that 12 pins of that bank are being occupied for the ADC) with ADC signals working at 500 MHz .

Now , Suppose I  can choose freely the banks 34 and 33  of the FPGA without problem for the DDR3. But as I above mentioned the bank 33 is full with ADC signals.So I need to relocate them.  What if I have available an HR bank, can I relocate all the ADC signals I actually have in the  HP bank 33 to one HR bank? .meaning that now, the banks for the ADC are the 32 which is HP, and one of the HR banks.

Which problems will surge with the ADC signals being mapped to one HP and one HR bank? how can I deal with them?

 

-FPGA part:  xc7k160tffg

-The ADC part is: ADC12D500RF 

ADC datasheet : http://www.ti.com/lit/ds/symlink/adc12d500rf.pdf

- The differential data from the ADC is just received at the FPGA, passed through an IBUFDS and then stored into a FIFO.

 

@drjohnsmith has given there  a first answer to this post. thank you.

 

More opinions will be very usefull to make richer this discussion.

 

Thank you.

0 Kudos
17 Replies
Highlighted
Explorer
Explorer
954 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

In Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics , pg 14, table 17 . There are specified performance characteristics for some implemented designs, specifiyng bank type; HP and HR banks. The worst case value performance around 710 Mbps would indicate I can use and HR bank together with and HP bank, without problem, at least refered to speed. What do you think?

 

link Kintex-7 FPGAs Data Sheet: DC and AC Switching Characteristics : https://www.xilinx.com/support/documentation/data_sheets/ds182_Kintex_7_Data_Sheet.pdf

0 Kudos
Explorer
Explorer
900 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

Additionally, in the WP393 it is stated in page 4.      "The HR I/O banks are designed to support a wider range of I/O standards, with voltages up to 3.3V. The HR I/O banks are optimized for the broadest range of application coverage while still achieving DDR3 interface speeds up to 1,066 Mb/s. They also address LVDS interfaces at up to 1,055 Mb/s. The I/O in this bank type are compatible with modern and legacy interfaces."

meaning that for LVDS interfaces I can have up to 525 MHz in my application. I want the ADC working at 500MHz. But I don't know if there is something else I need to have into account.

 

 

0 Kudos
Highlighted
Teacher
Teacher
889 Views
Registered: ‎07-09-2009

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

Hi

You have been on this a while,  

The way to handle all these questoins, is to try a test case,

 

The FPGA tools are free , 

    make a test  example, see if you can capture the adc data ,

        try with a test bench, 

            try putting the data into an ILA on the FPGA, and see if you can meet timing,

     Do the same for the memory, 

        you will learn a lot more from a few days experimenting, and all the work will be reusable n the product, than 100 posts to the forums, 

Sorry , its been a long day, but the above is called engineering, the more you practice the divide and conquer 

 

Regarding that ADC,

    meeting the timing requirements in realaity is very difficult and would be a test for an experienced engineer, 

    At these 500 MHz frequencies, the tracks have to be electrically length matched to 10's of ps accuracy, they need to be routed due care for track impedance matching, no vias etc.   If any of the above is a surprise to you, then take a big step back,

You need to use the Clk signal supplied with the data to capture the data at the FPGA to have a hope of capturing reliable data. 

Its because of all these problems that ADC's and DACs have gone over to the much easier to use JESD204 B interface. 

 

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
Highlighted
853 Views
Registered: ‎01-22-2015

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

@jose09621 

I can see that you are using Vivado to check out all aspects of a newly planned board.  That's just what we all should do, but sometimes don't.  Kudos to you for doing it the right way.  When planning a new board, be sure to read chapter 2 in UG949 and read as much of UG483 as you can stand.

My quick read of the ADC datasheet shows that you have a 12-bit parallel, SDR-or-DDR, source-synchronous interface with the ADC.   An interface with SDR=500MHz/DDR=250MHz is really fast!   So, you next should read Avrum’s posts <here> and <here> to determine whether the interface is doable from a timing point of view.  

Mark

 

Highlighted
801 Views
Registered: ‎01-22-2015

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

@jose09621 

Which problems will surge with the ADC signals being mapped to one HP and one HR bank? how can I deal with them?

First, you'll need to send a low-jitter clock to the sampling clock (CLK+/-) inputs of your fast ADC otherwise the Effective Number Of Bits (ENOB) will not be 12-bits.  Do not generate a clock in the FPGA and send it to CLK+/-, because FPGA-generated clocks have too much jitter for this use.

Your ADC has lots of LVDS outputs and maybe some LVDS inputs.  So, using HP banks with VCCO=1.8V will work best for you.  However, using LVDS in HR banks can be a challenge.  If VCCO=2.5V then you can use LVDS_25 as indicated in Table 1-55 of UG471(v1.10).  Comparing Tables 12 and 13 in DS182 for LVDS_25 and LVDS, you will find that VODIFF, VOCM, VIDIFF, VICM are identical.  So, LVDS and LVDS_25 are very compatible with each other – and I think you will find them to be compatible with the LVDS clock and data outputs of the ADC (but you’ll need to check this).  If you plan to use a value other than 2.5V for VCCO in and HR bank then you will have trouble with LVDS.  For VCCO > 2.85V you can only get LVDS input (and not LVDS output) and only with special external circuitry as described on pages 92-93 of UG471.  For VCCO < 2.5V in HR bank, I’m not sure what LVDS-like options are good for you.  You can try looking through Table 1-55 of UG471 to see which differential IO standards are allowed and then go to DS182 to check that VODIFF, VOCM, VIDIFF, VICM are compatible with LVDS outputs of your ADC.

Next, you should think about a clocking architecture in the FPGA for capturing the ADC data. Since, you are working in multiple banks/clocking-regions then you have what is called Multi-Region Clocking (see Appendix A in UG472).  These clocking schemes are good for capturing high-speed data but work only when the banks are vertically adjacent to each other.  In the XC7K160T, all the HP banks are on the right-side of the die and all the HR banks are on the left-side of the die (see figure below from UG475). 

XC7K160T_banks.jpg

So, in the XC7K160T, there is no HP bank that is vertically adjacent to an HR bank.  However, you could pick two vertically adjacent HR-banks (eg. 12 and 13) and use LVDS_25 and use Multi-Region Clocking.  Specially, you can bring the data-clock (DCLK+/-) from the ADC into clock-capable pins on the FPGA and from there to a BUFMR.  The BUFMR can then drive BUFIO in both banks which in-turn drive registers/IDDR in the IOB that capture the ADC data.  The BUFMR can also drive BUFR in both banks which in-turn drive logic in the FPGA fabric that receives the ADC data from the IOB registers/IDDR.

As drjohnsmith says, you should try all of this using Vivado.  You’ll need to write constraints for the ADC interface (create_clock, set_input_jitter, set_input_delay).  Let us know if you need help writing these constraints – or, search the Forum for what Avrum recommends.

Highlighted
Explorer
Explorer
771 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

Hi markg@prosensing.com , first of all thank you for the links about the discussion, I'll have to view it in a detailed way because it contains some things I don´t know yet, but thank you for that. I think it can be useful.

 

Regarding to the LVDS standards, You are right, and I hadn't seen it yet, thank you for that. In the HR I can use the 2.5 V, so it wouldn't be a problem, and also the LVDS of the ADC is compatible with the information that there is in Tables 12 and 13 in DS182.

Regarding to the Multi-Region Clocking: reading what you say about, it made me think about what's happening in a project I am synthesizing in Vivado. I saw that I´m using a clocking wizard core which is feeded with an external clock (External clock-->IBUFGDS--->clocking wizard core) and that clock (output of the clocking wizard) is the one I hope works for the whole logic in the FPGA. I see that using that, basically infers between other things a BUFG that can reach several region in the FPGA. Same way, for the ADC clock, it reaches a clocking wizard that infers between other things a BUFG, as the process above.
If I stay with the use one HR and one HP, I think I can use the BUFG, but based in what you say it would be a limited design, if I need to use de BUFMR. What do you think about it? is it not a good practice to opt for the BUFG from your experience? (I'll see how I can choose banks in the same column to avoid other problems)

thank you for your opinions, are always helpful. I need to keep reading to undestand better this things.

Hi, @drjohnsmith  Would you be more specific with "make a test example, see if you can capture the adc data , try with a test bench, try putting the data into an ILA on the FPGA, and see if you can meet timing" How can I simulate data capture in Vivado if I just have the pins that will be used for receive the ADC data? Thank you for the help.

0 Kudos
Highlighted
Teacher
Teacher
764 Views
Registered: ‎07-09-2009

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

what do you know about test benches ?
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
Highlighted
Explorer
Explorer
760 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

I've only done Behavioral simulations. I have some VHDL/Verilog module and excite the module inputs with the signals it is requering (clk, data, control), in order to verify that the behavior of the module is the one I hope.
0 Kudos
Highlighted
741 Views
Registered: ‎01-22-2015

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

@jose09621 

If I stay with the use one HR and one HP, I think I can use the BUFG…
You are correct!  The BUFG can drive any clocking point in the FPGA.  So, your idea of using (External clock-->IBUFGDS--->clocking wizard core-->BUFG) to clock logic in an HP bank and in an HR bank is a valid approach.  In the post <here>,  Avrum calls this approach “BUFG Capture with MMCM/PLL”.  The method I have proposed to you is what Avrum calls “Direct Capture with BUFIO or BUFR (ChipSync)” and it has the best timing.  Using Vivado, you can try both methods of capturing the ADC data by creating the necessary circuits, writing the proper timing constraints, and running implementation to see if the circuits pass timing analysis. 

In my opinion, understanding the design and timing constraints for these fast interfaces is one of the most difficult parts of FPGA work.  You are doing a great job!  -just hang in there and let us know if you need help.

Mark

Highlighted
Explorer
Explorer
706 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

markg@prosensing.com , really thank you for the help.  I'll study all that was brought to the post to understand better and then to design and evaluate the approaches with the timing analysis.

 

have a good day

0 Kudos
Highlighted
Explorer
Explorer
656 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

Hi markg@prosensing.com , Respect the LVDS and LVDS_25 discussion, I'd like to ask you something and see if I'm understanding correctly that part.

As you said,  in the Tables 12 and 13 in DS182 for LVDS_25 and LVDS we can see that the parameters  VODIFF, VOCM, VIDIFF, VICM are identical. It is just different the VCCO voltage. 

My doubt is with what say in UG471 in the page 92.  "It is acceptable to have differential inputs such as LVDS and LVDS_25 in I/O banks that are powered at voltage levels other than the nominal voltages required for the outputs of those standards (1.8V for LVDS outputs, and 2.5V for LVDS_25 outputs). However, these criteria must be met"

So, If I have some  LVDS (1.8V) from my ADC, as input to one HR (VCCO=2.5V), does it mean that if I want to do that  I need  to use the  external circuit (Figure 1-72, page 93) that both AC-couples and DC-biases the input signals?  I'm a bit confused with that part because the values of the tables 12 and 13 are identical.

 

thank you

0 Kudos
Highlighted
642 Views
Registered: ‎01-22-2015

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

@jose09621 

So, If I have some  LVDS (1.8V) from my ADC, as input to one HR (VCCO=2.5V), does it mean that if I want to do that  I need  to use the  external circuit (Figure 1-72, page 93) that both AC-couples and DC-biases the input signals?

In the case you describe, the external circuit shown in Fig 1-72 is not needed.  -just connect the wires directly from the ADC to the FPGA.

The thing to remember for an LVDS interface is that the transmitter/output specs (VODIFF, VOCM) must be compatible with the receiver/input specs (VIDIFF, VICM) – and there should be a termination (100 ohms) across the LVDS lines at the receiver end. 

As we discussed, IOSTANDARD=LVDS in an HP-bank with VCCO=1.8V is very compatible with IOSTANDARD=LVDS_25 in an HR-bank with VCCO=2.5V.  Let’s call these two cases IDEAL LVDS.  When using IDEAL LVDS, you can activate a 100-ohm termination internal to the FPGA when the FPGA is the receiver (see IBUFDS attribute DIFF_TERM=TRUE in Table 1.44 of UG471).

The FPGA can be a LVDS transmitter only if you are using IDEAL LVDS.

The statement you found on page 92 of UG471 says that the FPGA can sometimes be a LVDS receiver if you are not using IDEAL LVDS.  Pages 92-93 in UG471 explain how you can use circuits external to the FPGA to make this happen.

The following answer records have decisions trees that some find helpful when working with LVDS.

https://www.xilinx.com/support/answers/43989.html

https://www.xilinx.com/support/answers/40191.html 

Mark

Highlighted
Explorer
Explorer
596 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

Hi markg@prosensing.com , thank you for answer. 

As I understand  based in what you are saying,  and based on the answer records you provide me (there,  I also see, the 41408) maybe my problems can be solved more easily.

I mean, based on that,  I wouldn't even need to use both HR banks and HP banks ( i.e, in that case I can  use just  HP banks for the ADC).  I can use the free pins on the HP bank where I have the DDR3 memory.  The HP bank of the DDR3 memory has VCCO = 1.5 V , and the free pins I have in this bank can be used as  LVDS receivers for the remaining ADC signals I've been needing to locate. But, as those pins will be used as LVDS receivers, they need to use an external differential termination resistor, (External because DIFF_TERM just can be used if that bank would had VCCO= 1.8V, which is not the case). Additionally, as the VIN requirement (VIN < VCCO + 0.2V), the VIDIFF and VICM,  for those pins are satisfied, I don´t need anything else.  

Please Mark, confirm if this time I'm interpreting right.

One of the adventages I see with this is that I will have all my ADC interface in the same FPGA column. and with that making available the use of the BUFMR you mentioned.

0 Kudos
Highlighted
568 Views
Registered: ‎01-22-2015

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

@jose09621 

I am away from my computer until Monday but will try using my phone to give you some thoughts:

  1. AR41408 was a good find!  For Vin restriction, be sure to use max values of VOCM and VODIFF for LVDS output from the ADC.
  2. External AC coupling and rebiasing circuits will add signal delay that will need to be characterized.  If these circuits are used on some inputs and not others then interface may not work.  That is, for each ADC 12bit group, it is best that all LVDS traces from ADC to FPGA have equal delay.
  3. Need to check what FPGA resources are being used by DDR3 memory to ensure we aren’t prevented from using BUFMR+BUFIO (ChipSync).
  4. Your ADC is 2-channel, with separate 12-bit outputs for each channel and separate output data-clocks for each channel.  Can you fit data and data-clock for one channel in one bank and same for other channel in another bank?  If so then BUFMR approach is not needed.
0 Kudos
Highlighted
Explorer
Explorer
541 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

markg@prosensing.com , really thank you for your time. Please feel free to answer when you can, I don't want to bother you, and I can wait.

  1.  Why is it important to choose the max values of VOCM and VODIFF for LVDS output from the ADC?        -In the ADC (ADC12D500RF) the values I have been having into account  are:                                             VOCM    = 1.2 V             (there, The LVDS output common-mode voltage is specified as VOS  )      and   VODIFF  = 670 mVp-p   (there, LVDS Differential Output Voltage is specified as VOD)

NOTE:  above VODIFF  = 670 mVp-p, but in tables 12 and 13 of DS182, the max input value for VIDIFF for the LVDS and LVDS25 standards is  VIDIFF = 600 mV.  A violation as  I  actually have it?

   2. In the next diagram from the  43989 , I show with the green arrows the steps I think are the correct

diagram_LVDS.png

As I mentioned, the VCCO = 1.5 V . So, for the Vin requirement evaluation I have

                                                    TxVOCM   + TxVOD/2    < VCCO + 0.2 V

                                                        1.2V      +   670mV /2  < 1.5 V + 0.2 V

                                                                               1.535 V < 1.7 V

this result shows that the Vin Requirement is fulfilled. So, I can pass to the last step, bounded by the green line. There, it says I need the board termination (Because in this case, with VCCO != 1.8V I cannot use DIFF_TERM) but in this step I don't need  the AC-couple and DC-bias circuit. So, why do you refer to the AC-couple and DC-bias circuit ? 

Note: As mentioned in the first note, the VODIFF  = 670 mVp-p  of the ADC is violating the range for the VIDIFF in the LVDS tables. So I would fix it to a lower value like 500mV

Regarding points 3 and 4, I'll need to see those with more detail, I'll let you know about it as soon as I have the proper answer for those points.

 

Really thank you so much, for share your knowledge about this topic.

0 Kudos
Highlighted
432 Views
Registered: ‎01-22-2015

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

@jose09621 

Why is it important to choose the max values of VOCM and VODIFF for LVDS output from the ADC?
1) DO NO HARM: By definition, an LVDS transmitter (eg. your ADC) can place a maximum voltage on either LVDS line equal to [max(VOCM) + max(VODIFF)/2].  An LVDS transmitter can place a minimum voltage on either LVDS line equal to [min(VOCM) – max(VODIFF)/2].  Your first consideration when sending LVDS signals to the FPGA is to “do no harm”.  This means that the max/min LVDS line voltages cannot exceed the “Absolute Maximum Ratings” for Vin found in Table 1 of the datasheet (DS182) for your FPGA (Kintex-7) – otherwise you can damage the FPGA.  Further, if you want the FPGA inputs to work properly, then you must also ensure that the max/min LVDS line voltages do not exceed the “Recommended Operating Conditions” for Vin found in Table 2 of DS182.

A violation as I actually have it?
2) ADJUSTABLE LVDS:  You are correct!  Some settings for the ADC give LVDS outputs that exceed the VIDIFF specification for LVDS shown in Tables 12 and 13 of DS182.  However, your ADC has adjustable LVDS outputs.  If you set VBG=VA and OVS=Low, then Table 3.10 of the ADC datasheet shows VODIFF=VOD=(500mV typ) and VOCM=VOS=(1.2V typ).  I recommend that you ask the ADC manufacturer for max/min values of VOD and VOS when VBG=VA and OVS=Low.  Then, as I described in 1) above, you should check that the LVDS voltages meet Vin specs in Table 1 and in Table 2 of DS182 – and meet LVDS specs in Table 12 and Table 13 of DS182.  Then, you can again go through the LVDS decision tree in AR#43989 to see where things end up.

So, why do you refer to the AC-couple and DC-bias circuit ?
3) AC-COUPLING AND DC-REBIASING:  -of LVDS can be used for clock signals.  However, it cannot generally be used for data signals.  This is because the AC-coupling will prevent the transmission of constant data – unless you use special data encoding schemes (eg. Manchester encoding).  I don’t recommend using “AC-coupling and DC-rebiasing” for your project – and I don’t think you need it.  However, you can use termination resistors that are external to the FPGA if you are prevented from using termination resistors that are internal to the FPGA.

4) ADC INTERFACE COMPATIBLE WITH MEMORY INTERFACE:  As you put together your project in Vivado, Vivado will tell you whether there are FPGA-resource conflicts between the ADC interface and the external SDRAM interface.

5) USING CHIPSYNC:  As I and Avrum mentioned, the ChipSync method of data capture has the best timing.  You can use ChipSync to capture the ADC data if all clock and data inputs from the ADC can be located in two or three vertically adjacent IO banks of the FPGA.  In this way, a BUFMR is used to spread a ChipSync interface across the two/three banks. However, ChipSync will work even better if you do the following:  a) place the data-clock-output and the 12 data-outputs from ADC channel-A in one IO bank of the FPGA, b) place the data-clock-output and the 12 data-outputs from ADC channel-B in another IO bank of the FPGA.  These two banks need not be vertically adjacent – since each bank can use its own independent version of ChipSync.

Highlighted
Explorer
Explorer
380 Views
Registered: ‎02-13-2019

Re: ADC signals distributed in one HP bank and one HR Bank (making banks available for the DDR3)

Hi , markg@prosensing.com . thank you for answer.

regarding to:

1) DO NO HARM: Well, It seems I some kind misunderstood what you meant in the post before the "DO NO HARM" explanation (I thought I had to choose as output the max possible values for my final configuration). But now with your explanation, I understand, I must have into account the extreme values to make sure my configuration "do no harm" the FPGA device.

2) ADJUSTABLE LVDS:  I sent my request asking the ADC manufacturer for max/min values of VOD and VOS when VBG=VA and OVS=Low, in order to make the  correct calculations and fulfill the "do no harm" conditions  for the Vin specifications and the LVDS specifications. So I guess, I'll have to wait for that information and then assess again the LVDS decision tree.

3) AC-COUPLING AND DC-REBIASING: This is a very important clarification Mark, thank you a lot for that. Though  in the UG471 This circuit is shown for a clock input there is no clarification about data signals, neither in the LVDS decision tree of AR43989.

4,5) Ok Mark,  I'll proceed with Vivado, and to see what it says about having the SDRAM interface and the ADC interface. You've help me to widen my user options about LVDS standards in different banks, and how are related some clock architectures with the banks the user chooses. Definitely, I'll have into account what you say about ChipSync with ADC channels in independents banks.

 

Mark, really thank you for the help, I've learned from this post very important things from which I was not even conscious yet. 

 

0 Kudos