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Contributor
Contributor
7,524 Views
Registered: ‎04-09-2015

AXI Interconnect WREADY is high before MIG WREADY

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Hello everyone,

 

I have a MIG IP Core (v1.8) and an AXI Interconnect with one Master Interface to the MIG and several Slave Interfaces to connect peripherals to it.

 

The AXI-Interconnect asserts WREADY before the connected MIG Core asserts WREADY.

Is that intended behaviour?

 

Cheers,

Steffen

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Contributor
Contributor
13,863 Views
Registered: ‎04-09-2015

Re: AXI Interconnect WREADY is high before MIG WREADY

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Nevermind.

I regenerated the AXI Interconnect Core and found out that clock conversion was set to 1:2 what should be 1:1.

Still find it interesting that the READY signals are asserted with clock conversion included. Should that be the case?

 

Cheers,

Steffen

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Xilinx Employee
Xilinx Employee
7,499 Views
Registered: ‎08-02-2011

Re: AXI Interconnect WREADY is high before MIG WREADY

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Hi Steffen,

It seems reasonable to me, particularly if you've enabled buffers or register slices inside the interconnect.

 

What's your concern about it? 

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Contributor
Contributor
7,432 Views
Registered: ‎04-09-2015

Re: AXI Interconnect WREADY is high before MIG WREADY

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Hmmm.... that's the thing.

I haven't enabled any buffers, FIFOs or register slices for the interconnect.

Coming from the AXI4 specifications it makes sense to keep WREADY high to enable the chance for a direct data transfer.

 

My problem at the moment:

When I issue a data transfer to the MIG via Interconnect first of all I transfer the burst information via AW-channel.

Then I assert the WVALID and look for the WREADY to become asserted so I can start transferring consecutive data-words.

WREADY is high until 3 clock cycles after I transfered the burst information via AW-channel (meaning I also transfer 3 data-words within that time).

WREADY then goes low for 3 clock cycles and comes back high again (which pauses the data transfer for 3 clock cycles, no problem).

 

In general this wouldn't be a problem but when I want to read the data that I just wrote to the MIG, I receive nothing but rubbish.

 

I wonder if it is intended behaviour for the AXI interconnect to receive AW/AR-channel information, forward them to the MIG and be ready on the W/R-channel only 3 clock cycles after issuing the burst information (since WREADY runs through one high-low-high-cycle)?

 

Cheers,

Steffen

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Contributor
Contributor
7,430 Views
Registered: ‎04-09-2015

Re: AXI Interconnect WREADY is high before MIG WREADY

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Quick note: It would make sense to me, if I had FIFOs or register slices enabled, because then the Interconnect could buffer my datawords before sending them out to the MIG. Since I didn't include them in the interconnect (at least I told the Core Generator to do so) that behaviour kinda puzzles me.
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Contributor
Contributor
13,864 Views
Registered: ‎04-09-2015

Re: AXI Interconnect WREADY is high before MIG WREADY

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Nevermind.

I regenerated the AXI Interconnect Core and found out that clock conversion was set to 1:2 what should be 1:1.

Still find it interesting that the READY signals are asserted with clock conversion included. Should that be the case?

 

Cheers,

Steffen

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