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Observer
Observer
10,489 Views
Registered: ‎09-21-2011

AXI MIG Virtex-6 4KB Burst Boundary

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I have seen this post verifying that crossing 4KB boundaries violates the ARM AXI spec.

http://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/m-p/216413/highlight/true#M5924

 

And this post indicating that Spartan-6 AXI Memory Controller does not support (or prevent) 4KB boundary crossing:

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Burst-on-axi-s6-ddrx-info/td-p/274670

 

However, the corresponding V6 Memory Interface Solutions User Guide (ug406) does not state a warning on crossing 4 kB boundaries, nor does it state any explicit support for crossing 4 kB boundaries.  Simulation shows that requesting a burst that crosses 4 kB boundaries does not alter the results or return unexpectedly.

 

Does the V6 AXI4 memory controller generated by MIG 3.8 officially support or not support 4KB-unaligned bursts?

 

 

Thanks,

JoRyTe

 

 

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Xilinx Employee
Xilinx Employee
17,543 Views
Registered: ‎07-11-2011

Hi,

 

AXI MIG supports unaligned burst transfers but as per protocol burst must not cross 4KB boundry.

 

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Xilinx Employee
Xilinx Employee
17,544 Views
Registered: ‎07-11-2011

Hi,

 

AXI MIG supports unaligned burst transfers but as per protocol burst must not cross 4KB boundry.

 

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Observer
Observer
10,452 Views
Registered: ‎09-21-2011

Thanks.  Can you point me to some Virtex-6 relevent Xilinx documentation warning against crossing 4 kB boundaries when bursting for future reference?

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Xilinx Employee
Xilinx Employee
10,449 Views
Registered: ‎07-11-2011

Hi,

 

As no more ISE releases were planned, I don't think existing 6 series documents would get updated, I will put this info in an AR and try to publish it

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Observer
Observer
10,446 Views
Registered: ‎09-21-2011

Excellent, Thanks!  If you remember, please post the AR to this message for future reference.

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