AXI interface for RLD3

[dave_lautzenheiser]

Working on a demonstration design using the VCU110 and want to have some bulk storage for an embedded microblaze. As there is no conventional DRAM on the board, it seems that perhaps using the RLD3 is a way to get some significant storage.

Is anyone aware of an AXI interface to the MIG core that can be generated for the RLD3 on the VCU110?

Thanks

PS - using 2017.2 at the moment

[mcertosi]

Hi @dave_lautzenheiser

I just looked through the tools, there is no AXI shim for the RLD3 or QDR II+ IP. This makes sense because these are both reduced latency controllers and in applications that require reduced latency AXI is not always the optimal choice. You could take a look at our example design and use that as a guide to interface to the RLD and QDR IP. 

I can't think of a reasonable way to do this with our out of the box tools, however the Native interface for the DDR IP and the RLD IP is very similar. Since the shim isn't encrypted you could try to connect them.

That's what I can think of right now, what do you think about that? 

-Matt 

[mcertosi]

@ryana Can you help out with your XHMC experience? 

@dave_lautzenheiser - I was thinking my first answer may not have included the XHMC memory. You might be able to use the AXI interface with the XHMC IP and the HMC memory on the VCU110

[ryana · Accepted solution]

Hello @dave_lautzenheiser,

The VCU110 does have a 2GB Hybrid Memory Cube (HMC) stack on the board with an AXI interface option.  This will probably work just fine for what you need to do.

Here's a link to the product IP page:

https://www.xilinx.com/products/intellectual-property/ef-di-xhmc.html

Here's a link to the XHMC IP documentation:

https://www.xilinx.com/support/documentation/ip_documentation/xhmc/v1_0/pg216-xhmc.pdf

[dave_lautzenheiser]

Thanks!

HMC investigation a couple of months ago went nowhere because of availability. This looks like it will work providing I can get the right license to the IP.