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Adventurer
Adventurer
362 Views
Registered: ‎04-29-2018

AXI4 PL-DDR4 MIG Address mapping

I am using ZCU102 board, able to read/writes to the onboard PL-DDR4 memory using AXI4 interface.

I am trying to understand, if there is a way for me to specify what Row,Col,Bank address to be tested using AXI4 addressing..?

Basically 4Gb memory is mapped to "400000000 to 41FFFFFFF" address space. For example, if i write some data onto a particular location 4xxxxxxxx. Is it possible for me to decode what row,col,bank it's written to..?

 

 

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Xilinx Employee
Xilinx Employee
333 Views
Registered: ‎08-21-2007

回复: AXI4 PL-DDR4 MIG Address mapping

The address mapping options for PLL-DDR4 are ROW_COLUMN_BANK, ROW_BANK_COLUMN and BANK_ROW_COLUMN. If you would like to access particular address, you have to reorganize the user address input.