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tomray
Observer
Observer
8,631 Views
Registered: ‎03-27-2014

About the timing constrain for MIG 7 Series

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In my design, I use three DDR3 memory controllers generated by MIG 7 Series 1.6. The memory working frequency is 800MHz, so for BL8 the memory controller working frequency is 200MHz. It means that c0_clk, c1_clk, c2_clk must be 200MHz ? There is no constrain for these three clks in the UCF generated by MIG 7. So I add the constrain in UCF file as follows:

##200MHz

NET "c0_clk" PERIOD = 5 ns HIGH 2.5 ns;

##200MHz

NET "c1_clk" PERIOD = 5 ns HIGH 2.5 ns;

##200MHz

NET "c2_clk" PERIOD = 5 ns HIGH 2.5 ns;

 

I don’t know whether the constrain I add above is necessary or not. Anyone has any idea ?

 

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tomray
Observer
Observer
13,151 Views
Registered: ‎03-27-2014

Thanks very much. I will clear these additional constrains and have a try.

View solution in original post

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vsrunga
Xilinx Employee
Xilinx Employee
8,627 Views
Registered: ‎07-11-2011

Hi,

 

I think you are referring user clocks.

MIG has MMCM and PLL that derive required clocks and the constraints will be automatically prpogated based on system clock period.

So no additionaly constraints are needed.

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tomray
Observer
Observer
13,152 Views
Registered: ‎03-27-2014

Thanks very much. I will clear these additional constrains and have a try.

View solution in original post

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