11-09-2014 08:18 PM
In my design, I use three DDR3 memory controllers generated by MIG 7 Series 1.6. The memory working frequency is 800MHz, so for BL8 the memory controller working frequency is 200MHz. It means that c0_clk, c1_clk, c2_clk must be 200MHz ? There is no constrain for these three clks in the UCF generated by MIG 7. So I add the constrain in UCF file as follows:
NET "c0_clk" PERIOD = 5 ns HIGH 2.5 ns;
NET "c1_clk" PERIOD = 5 ns HIGH 2.5 ns;
NET "c2_clk" PERIOD = 5 ns HIGH 2.5 ns;
I don’t know whether the constrain I add above is necessary or not. Anyone has any idea ?
11-09-2014 08:36 PM
I think you are referring user clocks.
MIG has MMCM and PLL that derive required clocks and the constraints will be automatically prpogated based on system clock period.
So no additionaly constraints are needed.