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akokha
Adventurer
Adventurer
285 Views
Registered: ‎07-08-2019

Access DDR within RTL Code

Hi,

I am good in writing RTL code using verilog & VHDL. But, I am new to Vivado Design Suite and have problems accessing off-chip DDR memory.

Suppose that we have two vectors of 16-bit numbers stored in off-chip DDR memory (length of each vector is vlen). I want to write a verilog module that adds these vectors up and stores the resulting vector back into the off-chip DDR memory.

module addvec(
   input  clk,
   input  start,
   input  [7 :0] vlen,
   input  [15:0] veca,
   input  [15:0] vecb,
   output [15:0] vecout,
   output ready
);

 

I don't have any problem with the design and coding of the computation engine.

How can I interface this module to DDR memory? (My target FPGA family is Virtex7)

 

(Please don't refer me to a 300-page Xilinx tutorial generally! I tested some of them. But, they are confusing to me, because of various prerequisites and references inside)

 

Many thanks in advance,

Ali

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2 Replies
kren
Moderator
Moderator
247 Views
Registered: ‎08-21-2007

You need to create logic to write these data into certain address of the DDR memory. You can learn the timing on the user interface of MIG controller according to the correspoding section in ug586.

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akokha
Adventurer
Adventurer
206 Views
Registered: ‎07-08-2019

Thanks @kren ,

I have read the first chapter of ug586 (pg. 1-90) and created the MIG interface multiple times. Some parts are clear and straightforward, but others are somewhat vague. There are a lot of files/modules, parameters and signals many of which seem unnecessary. Sometimes, they are confusing rather than helpful!

I could not find that which files I need to add to my project in order to simulate/synthesize my design. Which parts of the example_design are not needed, and so on. Which module must be replaced with my core module (eg., addvec here)?

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