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Adventurer
Adventurer
14,557 Views
Registered: ‎11-10-2009

Artix-7 DDR3 driver needs a lot of resources

Hello all,

 

I have been dealing in the last weeks with the integration of a DDR3 memory in my design. I want to access this directly from my FPGA logic and thus I created a driver with MIG.

 

My surprise came when I saw the resources usage of such driver. Around 20% of the whole FPGA! (See attached image)

I remember in Spartan-6 there was an integrated MCB which dealt with most of the interfacing work to the DDR3 and the logic usage for an equivalent driver was around 10 times smaller.

 

Is there a way to create a more reasonable driver for this part? Am I maybe doing something wrong?

I am afraid that, in case it is not like this, I will have to use a SDRAM, which I initially did want to avoid.

 

The actual configuration of my MIG is the following:

 

Vivado Project Options:
   Target Device                   : xc7a35t-fgg484
   Speed Grade                     : -2
   HDL                             : vhdl
   Synthesis Tool                  : VIVADO

If any of the above options are incorrect, please click on "Cancel", change the CORE Generator Project Options, and restart MIG.

MIG Output Options:
   Module Name                     : integration_interface
   No of Controllers               : 1
   Selected Compatible Device(s)   : --

FPGA Options:
   System Clock Type               : Single-Ended
   Reference Clock Type            : Use System Clock
   Debug Port                      : OFF
   Internal Vref                   : enabled
   IO Power Reduction              : ON
   XADC instantiation in MIG       : Disabled

Extended FPGA Options:
   DCI for DQ,DQS/DQS#,DM          : enabled
   Internal Termination (HR Banks) : 50 Ohms
   
/*******************************************************/
/*                  Controller 0                       */
/*******************************************************/
Controller Options :
   Memory                        : DDR3_SDRAM
   Interface                     : NATIVE
   Design Clock Frequency        : 2500 ps (  0.00 MHz)
   Phy to Controller Clock Ratio : 4:1
   Input Clock Period            : 5000 ps
   CLKFBOUT_MULT (PLL)           : 4
   DIVCLK_DIVIDE (PLL)           : 1
   VCC_AUX IO                    : 1.8V
   Memory Type                   : Components
   Memory Part                   : MT41J256m16XX-125
   Equivalent Part(s)            : MT41J256M16HA-125
   Data Width                    : 8
   ECC                           : Disabled
   Data Mask                     : enabled
   ORDERING                      : Normal

AXI Parameters :
   Data Width                    : 64
   Arbitration Scheme            : RD_PRI_REG
   Narrow Burst Support          : 0
   ID Width                      : 4

Memory Options:
   Burst Length (MR0[1:0])          : 8 - Fixed
   Read Burst Type (MR0[3])         : Sequential
   CAS Latency (MR0[6:4])           : 6
   Output Drive Strength (MR1[5,1]) : RZQ/7
   Controller CS option             : Disable
   Rtt_NOM - ODT (MR1[9,6,2])       : RZQ/4
   Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off
   Memory Address Mapping           : BANK_ROW_COLUMN


Bank Selections:

System_Clock:
 SignalName: sys_clk_i
  PadLocation: C18(MRCC_P)  Bank: 16

System_Control:
 SignalName: sys_rst
  PadLocation: No connect  Bank: Select Bank
 SignalName: init_calib_complete
  PadLocation: No connect  Bank: Select Bank
 SignalName: tg_compare_error
  PadLocation: No connect  Bank: Select Bank

 

   

mig_artix_7_resources.jpg
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6 Replies
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Professor
Professor
14,525 Views
Registered: ‎08-14-2007

The Spartan-6 had an MCB because frankly it was not fast enough to handle this sort of interface with the native fabric.  Artix is much more flexible in that you can create a memory interface of different sizes and still run at a higher frequency than the Spartan-6 MCB.  It does not seem unreasonable that MIG takes up 20% of one of the smaller members of the Artix series.  The question is whether the other 80% of the part is enough to accomplish your design.  MIG 7-series can seem especially big for a small external memory like a single by-8 chip.  It doesn't get a lot bigger when creating a larger memory, because most of the logic is in the control rather than the data path.  Not sure if that helps in your case, though.

 

I'm not sure what you meant by "I am afraid that, in case it is not like this, I will have to use a SDRAM, which I initially did want to avoid."  Did you mean the old single data rate SDRAM? or was it a typo and you meant SRAM?  SRAM would use a lot fewer internal resources, but require a lot more I/O's.

-- Gabor
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Adventurer
Adventurer
14,505 Views
Registered: ‎11-10-2009

Hi Gabor,

 

thank you very much for your rapid answer.

 

I can understand why Spartan-6 needed the extra MCB but I cannot believe that it is just impossible to have applications with a decent external RAM in the smallest devices, where Spartan-6 did not have any problem with. 80% of the FPGA would be maybe enough but further than 70% of the usage it starts being tricky to fit all the functionality without severe timing issues (actually I misstyped here, I wanted to say that the DDR3 driver takes 25% of the resources).

 

For some of us, upgrading to the next bigger device is a no-go. My application has some quite tight specifications regarding costs and I can, unfortunately, not spend 50% more on a FPGA just for this single feature.

 

I intend to do some fast data logging for a scope functionality and the internal BRAMs are not enough. I had no problem with the previous Spartan-6 25K but it seems that Artix-7 is a clear step back in this case.

 

Regarding to the SDRAM yes, I meant SDRAM (the old ugly single data rate device). I supposed that it would take far less logic in the FPGA to create a driver for it. Unfortunately I have just discovered that MIG does not support these devices for the 7 Series and I should create a driver on my own.

 

I do not really need the 4 Gbits of my DDR3 for logging. A couple 256 Mbit SDRAMs could work but having to type the driver for it is another ugly fact.

 

Maybe I am missing what could be an easier and silicon-cheaper solution for interfacing with an external RAM device (no SRAM). Does anybody have any idea here?

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Professor
Professor
14,489 Views
Registered: ‎08-14-2007

If the Spartan 6 LX25 worked for you, why are you switching to Artix-7?  It looks like the pricing is pretty similar to the part you're working with now.  Also single-data-rate SDRAM is much slower than DDR3, so you'd need to either use a lot more IO pins or live with a much lower memeory bandwidth.  What's your external memory bandwidth requirement?

-- Gabor
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Adventurer
Adventurer
14,346 Views
Registered: ‎11-10-2009

Hi Gabor,

 

we are switching because our application makes a very intensive use of DSP resources and BRAMs and here is Artix-7 clearly better.

 

Now we need to write in the memory at 40 MBytes/s in the worst case. The problem with SDRAM is the lack of support from Xilinx in the 7 Series :/

 

It does not have to be SDRAM or DDR3. Anything which has a reasonable memory depth (more than 64 MBytes), the above indicated speed and reasonable development effort with the driver can work.

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Professor
Professor
14,331 Views
Registered: ‎08-14-2007

I'm not sure if this is still the case for 7-series, but earlier versions of the EDK's MPMC (multi-port memory controller) had more options than MIG for external devices.  In fact MIG never supported single data rate SDRAM, but the MPMC did.  If you want to roll your own interface, LPDDR (not -2 or -3) SDRAM, originally called "mobile DDR", is about as easy as the original single-data rate memory and comes in larger formats including 32M by 16.  This type of memory does not need calibration to run at your required speeds, and can be slowed down because it doesn't include dynamic interface circuitry like DLL.  It also uses standard 2.5V LVCMOS rather than SSTL, making the interfacing simple as long as you don't place it too far from the FPGA.

The cheapest memory devices that have 64 Mbytes (512 Mb) or more are actually NAND flash.  The problem is that even with SLC NAND you'd need about 8 of them to get your required write bandwidth due to page write timing.  They also require more effort because you'd need to implement error detection and correction, and bad block management.  I've done this before for video recording equipment, but it's probably more effort than you want to get into for your project.  Not to mention that at that point you might save money by going to the next size FPGA and sticking with DDR3.

-- Gabor
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Adventurer
Adventurer
14,161 Views
Registered: ‎11-10-2009

Thank you very much but it seems like the EDK MPMC is not available for the 7 Series: http://www.xilinx.com/products/intellectual-property/mpmc.html

 

Indeed, in a tutorial provided by Xilinx they indicate how to build a MPMC with the MIG core plus an AXI interconnection: http://www.xilinx.com/support/documentation/application_notes/xapp1164.pdf

 

Unfortunately it looks that I will have to code by hand a driver for a SDRAM (or maybe a LPDDR).

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