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1,414 Views
Registered: ‎07-28-2017

Artix 7 FPGA with DDR3

Hi,

 

 I need DDR3 Timing specification for Artix-7 FPGA for SI analysis. 

 

Please provide the Documents or .V model and do the needful.
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Scholar
Scholar
1,399 Views
Registered: ‎08-07-2014

Hello,

 

the documents I guess, you can easily get via a search.

 

For a .v model of the DDR3, you have to work a bit.

Have Vivado Webpack installed. Generate a MIG core with DDR3 interfacing. From Vivado project, right-click on the generated core and create its example_design. Inside that example_design (this would be a new Vivado project), you find the DDR3 model.

------------FPGA enthusiast------------
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Teacher
Teacher
1,350 Views
Registered: ‎07-09-2009

do you mean the timing from / to the artex ? 

 

what tool are you using for SI analysis ?

 

    the verilog file ( .v ) does not have the information for SI analysis,

 

 

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