09-13-2017 03:15 AM
09-13-2017 03:47 AM
the documents I guess, you can easily get via a search.
For a .v model of the DDR3, you have to work a bit.
Have Vivado Webpack installed. Generate a MIG core with DDR3 interfacing. From Vivado project, right-click on the generated core and create its example_design. Inside that example_design (this would be a new Vivado project), you find the DDR3 model.
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09-13-2017 12:34 PM
do you mean the timing from / to the artex ?
what tool are you using for SI analysis ?
the verilog file ( .v ) does not have the information for SI analysis,