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vicky28891
Observer
Observer
668 Views
Registered: ‎04-06-2021

Block RAM is not working (BRAM generated using core generator in ISE 14.7)

Hello everyone,

I am new to use Block RAM in FPGA.

I generated Block RAM using core generator and used that in my code. 

I give all required signals in testbench but memory is not updating. I dont know why.

Please help me in this regard.

For reference, I am attaching the vhdl code and testbench.

vicky28891_0-1619112406180.png

 

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10 Replies
bruce_karaffa
Scholar
Scholar
660 Views
Registered: ‎06-21-2017

I don't see you generating a clock in your testbench.  The BRAM needs a running clock.

vicky28891
Observer
Observer
649 Views
Registered: ‎04-06-2021

thanks for your reply. Sorry, I attached wrong file. even with clock this BRAM is not working.

Please help 

vicky28891_0-1619112718762.png

 

memory_simulation.JPG
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dgisselq
Scholar
Scholar
621 Views
Registered: ‎05-21-2015

@vicky28891 ,

Your test signals should be set on the positive edge of the clock.

Dan

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vicky28891
Observer
Observer
602 Views
Registered: ‎04-06-2021

thanks for your reply.

But which signals should be on positive edge of clock. You mean data and address (if you mean this I tried still not getting dout)

 

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dgisselq
Scholar
Scholar
595 Views
Registered: ‎05-21-2015

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vicky28891
Observer
Observer
592 Views
Registered: ‎04-06-2021

Sorry I didn't get this Because I have just used BRAM component 

How can I control that ??

Can you please help me to correct the code if you can ?? Because I didn't get how I can correct this code as I am using the code generated by core generator 

It will be very simple for you if you are using BRams

 

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bruce_karaffa
Scholar
Scholar
591 Views
Registered: ‎06-21-2017

Can you try writing to several addresses, deasserting the write enable and try to read from those same addresses?

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vicky28891
Observer
Observer
335 Views
Registered: ‎04-06-2021

tried this also but didnt get output from dout

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nofik92576
Newbie
Newbie
252 Views
Registered: ‎05-03-2021

Sorry I didn't get this Because I have quite recently utilized BRAM part How might I control that ?? Would you be able to if it's not too much trouble, assist me with adjusting the code in the event that you can ?? Since I didn't get how I can address this code as I am utilizing the code produced by center generator It will be straightforward for you in the event that you are utilizing BRams

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vicky28891
Observer
Observer
238 Views
Registered: ‎04-06-2021

hi nofik,

I am still stucked in BRAM as I am also new to use. Yes it is very straightforward . I am using FIFO generated by core generator. That is working very well. But in case of BRAM I dont know why I am not getting dout even everything looks correct.

Hope anybody will help on this.

and its very simple for check for those who worked on BRAM I don't know why people not replying not checking my code some people checked but its not solved yet.

 

Thanks

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