04-22-2021 10:17 AM - edited 04-22-2021 10:26 AM
I am new to use Block RAM in FPGA.
I generated Block RAM using core generator and used that in my code.
I give all required signals in testbench but memory is not updating. I dont know why.
Please help me in this regard.
For reference, I am attaching the vhdl code and testbench.
04-22-2021 11:40 AM
thanks for your reply.
But which signals should be on positive edge of clock. You mean data and address (if you mean this I tried still not getting dout)
04-22-2021 12:08 PM
Sorry I didn't get this Because I have just used BRAM component
How can I control that ??
Can you please help me to correct the code if you can ?? Because I didn't get how I can correct this code as I am using the code generated by core generator
It will be very simple for you if you are using BRams
05-03-2021 02:28 AM
Sorry I didn't get this Because I have quite recently utilized BRAM part How might I control that ?? Would you be able to if it's not too much trouble, assist me with adjusting the code in the event that you can ?? Since I didn't get how I can address this code as I am utilizing the code produced by center generator It will be straightforward for you in the event that you are utilizing BRams
05-03-2021 03:04 AM
I am still stucked in BRAM as I am also new to use. Yes it is very straightforward . I am using FIFO generated by core generator. That is working very well. But in case of BRAM I dont know why I am not getting dout even everything looks correct.
Hope anybody will help on this.
and its very simple for check for those who worked on BRAM I don't know why people not replying not checking my code some people checked but its not solved yet.