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Visitor
Visitor
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Registered: ‎02-02-2019

Block design with ILA for MIG example_design

Hi,

I wanted to verify MIG AXI based controller on FPGA board before putting into large design.

So, I opened example design in project and try to put example_top (top module) to block desing. But ended up with below message. Can you please let me know, how to resolve this?

[filemgmt 56-181] Reference 'example_top' contains sub-design file '*/*/*/mig_7series_axi4_ex/mig_7series_axi4_ex.srcs/sources_1/ip/mig_7series_axi4/mig_7series_axi4.xci'. This sub-design is not allowed in the reference due to following reason(s):
The 'xilinx.com:ip:mig_7series:4.1' core does not support module reference.

 

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Voyager
Voyager
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Registered: ‎03-28-2016

Re: Block design with ILA for MIG example_design

@raghavs 

It sounds like you tried to load the MIG example design as an HDL Module in a block diagram in IP Integrator.  I would be suprised if there was a way to make that work. 

Instead I would recommend recreating the design in IPI using the example design as a guide.  If you are using an eval board (ie ZCU102 or some other board), make sure that your Vivado project has the proper board files loaded for that board and make sure your project targets that board and not just the FPGA that is on that board.  The MIG requires detailed info about the DDR it is connected to in order to be properly configured.  Targeting the specific eval board should help Vivado to load the proper details for that board.

Ted Booth - Tech. Lead FPGA Design Engineer
https://www.designlinxhs.com
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Visitor
Visitor
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Registered: ‎02-02-2019

Re: Block design with ILA for MIG example_design

@tedbooth 

Thanks..Yeah, I have baseline design already tied to genesys2 board (pin mapping, constraint..etc).

I stopped exampled_design approach for now. Instead directly put ILA on baseline design which was working fine with NATIVE interface based MIG. Now I need AXI based MIC. I made sure DDR pins are properly mapped. But it did not work on FPGA..so Now, I generated ILA and connected probes on AXI signals..Hopefully, I should be able to debug something.

Since DDR side memory interface and timing is not changed, I wonder what can be the problem,as I verified AXI driver module that drives Memory controller in verilog simulations.

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