12-11-2019 09:36 PM
In our design using xilinx product with part number "XCZU47DR-2FFVE1156".
Need to run de-coupling analysis to ensure our designed PDN is well with in the limit.
From the datasheet it is not mentioned what is the frequency range should be consider for board level de-couling analysis (we are not including package and die parasitic).
Kindly provide the required information.
Vilas Kumar S
12-11-2019 10:08 PM
To be honest, Altera (Intel) has more information for design at the board level. I had been designing boards myself a couple of times and my target was to keep plane impedances low up to close to 100 MHz and expect no weird peaks up to 1 GHz.
12-11-2019 10:16 PM
I agree that usually board-decoupling should be taken care upto 100 MHz. But when i was perfroming the simulation for present design, the impedance plot was not meeting the requirement above 30MHz.
So, i need to know like from what frequency range the package de-coupling will acts.