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adieux
Contributor
Contributor
771 Views
Registered: ‎06-19-2017

CK to DQS skew constraint - UG583

We are designing a PCB with XCKU040 and a DDR4-2400 RDIMM. Our board designer is pulling his hair on meeting the skew constraints. 

One major problem for us is the CK to DQS skew constraint in Table 2-34 in UG583 page 87:

DQS-CK.png

The table gives +-150ps regarless of the DDR4 memory's operating speed. 

However, there are tables like this showing different skew constraints of cmd/addr to CK under different memory speeds (Table A-4, page 315):

CA-CK.png

 

We are wondering if there is also a table like the one above, showing different CK to DQS skew limits under different memory speeds

 

 

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3 Replies
watari
Teacher
Teacher
751 Views
Registered: ‎06-16-2013

Hi @adieux 

 

The purpose of these constraints are different.

So you must satisfy these constraints.

 

- Data to DQS

=> Use write and read access. Affect timing budget and bitrate.

- dqs_p and dqs_n

=> Use write and read access. Affect timing budget and bitrate. Get worse timing mergin if they are unblance.

- CK to DQS

=> Use write access and write/read leveling. Affect write leveling and read leveling, if you used fly-by or clamshell topology.

- CK to Address/Command/Control

=> Use all function. Most important constraint. Affect all function.

 

Best regards,

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adieux
Contributor
Contributor
708 Views
Registered: ‎06-19-2017

Yeah I understand the concepts of these constraints. 

The thing is, we've seen the skew limit increases as memory frequency decreases on DQ to DQS (Table A-3) and CMD/ADDR to CK (Table A-4). We are wondering if the CK to DQS skew will also increase as the memory frequency decreases?  

If this is true then we can relax our PCB design by lowering the mem frequency. 

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kshimizu
Xilinx Employee
Xilinx Employee
647 Views
Registered: ‎03-04-2018

Hello @adieux ,

 

Yes, your understanding is correct.  There is no other skew constraints regarding CK to DQS like TableA-4, hence please keep +-150ps.

 

Best regards,

kshimizu 

Product Application Engineer Xilinx Technical Support

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