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Observer viktorpus
Observer
9,595 Views
Registered: ‎08-19-2009

CQ bank placement

I have a question regarding the placing of CQ clocks within a bank of Virtex-7 device. I wonder if it is possible to place both positive parts of CQ signal (i.e. cq_p[0] and cq_p[1]) within a single bytegroup (bytelane) without violating the routing/placing rules. The bank is utilized as follows: bytegroup A and bytegroup B (i.e. T3 and T2) contains the data pins Q[18:35] clocked with CQ[0], bytegroup C and bytegroup D (i.e. T1 and T0) contains the data bits Q[17:0] clocked with CQ[1]. In addition to that, bytegroup C contains signal cq_p[0] connected to the P_MRCC pin and cq_p[1] connected to the  P_SRCC pin. The negative part of CQ (which is not utilized in the design) is connected to the MRCC/SRCC pins in bytegroup B.

 

According to the UG472 (7 Series FPGAs Clocking Resources), it should be possible to attach both cq_p[0] and cq_p[1] clock signals to the regional buffers (BUFR). These buffers should be able to distribute up to four clock signals across the whole bank. However, such a design fails with error "Place 30-174" that does not provide an exact reason (all the clock rules that are printed out are marked as passed). The same error is obtained if the cq_p[0] is attached to the BUFMR instance and cq_p[1] to the BUFR instance.

 

It seems that the routing to the PHASER_IN instances is somehow limited and only the BUMR buffers can be utilized even if it is not necessary to route the clock to the adjacent banks (i.e. out of a single bank). I suspect that the information about clock regions given in UG472 is somehow misleading or incomplete. Could you please clarify the rules? It is possible to utilize the mapping specified above or the cq_p[1] must be placed within bytegroup B and must be connected to a MRCC pin?

 

Thanks,

Viktor

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4 Replies
Xilinx Employee
Xilinx Employee
9,585 Views
Registered: ‎07-11-2011

Re: CQ bank placement

Hi,

 

This is Virtex-6 board but UG472 is 7 series clocking UG,  which device are you using V6 /7 series?

I assume you are using MIG and interfacing QDRII +SRAM device with Virtex-6 / 7series device.

If yes you should follow the pin placemenet guideliness given in UG406 - V6  and UG586 - 7 series.

  

Virtex-6 QDR pin placement rules.

 

QDRII_V6.png

 

If in case you are using 7 series refer QDR design /Pin requirements section from below UG

 

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf

 

 

Hope this helps.

 

Regards,

Vanitha. 

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Observer viktorpus
Observer
9,548 Views
Registered: ‎08-19-2009

Re: CQ bank placement

Hi,

 

I'm familiar with pinout requirements described in MIG user guide. As I stated above, we are using Virtex-7 FPGA. We have an FPGA card equipped with a QDR memory having two CQ clocks (MIG supports QDR-II with a single CQ clock only). Unfortunately, the user guides do not give any reason about the necessity to connect the CQ signals to MRCC pins.

 

Kind regards,

Viktor

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Observer viktorpus
Observer
9,501 Views
Registered: ‎08-19-2009

Re: CQ bank placement

Hi Vanitha,

 

is there any new information regarding this?

 

Regards,

Viktor

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Xilinx Employee
Xilinx Employee
9,443 Views
Registered: ‎07-11-2011

Re: CQ bank placement

Hi,

 

Rules is UG are deduced based on characterization results I am not sure the exact reasons behind each and evry rule but hope they were neded to support stated frequency.

Please point me to the user guide on QDRII+ with 2 CQ clocks, may be a request caould be placed to add those parts in future.

 

 

Regards,

Vanitha

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