12-04-2018 04:44 AM - edited 12-04-2018 04:45 AM
Can I swap adress pins of DDR3 on FPGA Artix-7 while routing traces on the board?
If yes, what pins can I swap? And please send me the guide, where it is described.
12-04-2018 05:41 AM
Look in UG586, 'Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.2' page 194:
Pin Swapping • Pins can be freely swapped within each byte group (data and address/control), except for the DQS pair which must be on a clock-capable DQS pair and the CK which must be on a p-n pair. • Byte groups (data and address/control) can be freely swapped with each other. • Pins in the address/control byte groups can be freely swapped within and between their byte groups. • No other pin swapping is permitted.
I suggest just recustomizing the MIG and see if Vivado will build a bitstream. That's the best authority.
12-04-2018 09:50 AM - edited 12-04-2018 09:53 AM
The guidelines in UG586 are in the context of the FPGA byte groups and overall everything's pretty flexible and the tools will flag an invalid pinout. The Bank and Pin Selection Guides for DDR3 Designs section starting on page 193 goes over these FPGA pinout expectations. However on the PCBA you cannot swap any address pins in the sense of mapping A0 to A3 or anything like that. Swapping address pin assignments on the DRAM side causes all sorts of issues with Mode Register settings and command protocol as it relates to Banks/Rows/Columns.