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Contributor
Contributor
8,520 Views
Registered: ‎12-08-2010

Can the DDR3 interface work ok, while the choosed BANKs spread across different Vccaux_io

Now, I am using XC7V690T-FFG1761I, and my DDR3 interface use BANK 35 36 37. These banks are in different VCCAUX_IO region: region 4 and region 5. All vccaux_io is 2.0v on my board.

 

When I generate the MIG core, the follow figure appear.

DDR3.jpg

 

Can the DDR3 interface work ok?

 

Thanks.

 

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Xilinx Employee
Xilinx Employee
8,390 Views
Registered: ‎07-11-2011

Re: Can the DDR3 interface work ok, while the choosed BANKs spread across different Vccaux_io

@xiangsong

 

It may work but with performance limitations, we do not have the quantative figures though.

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