09-21-2020 08:10 PM
I am working on a project to access DDR4 DRAM (64bit data width, 8GB) through DMA and MIG. The project is built based on the AXI DMA (direct access mode and tx/rx loopback) example. The project works fine for 32bit Microblaze and successfully access the DRAM via AXI bus (address 0x00000000~0xffffffff). However, when set Mircoblaze to 64bit and extend the AXI address to 35bit (64GB), if I set the DDR4 MIG address between 0x1_00000000 and 0x1_ffffffff, the Microblaze cannot work in correct mode and some errors are listed below:
1. After programming bitstream and launching .elf program, the software continuous running and cannot debug using breakpoint;
2. Via address monitor, I found that the data of correspond address (start from 0x1_01000000) changes to the values what I expect for the first access but DMA then return an error interrupt and then Microblaze stalls.
The DDR MIG windows and address editor is attached. The error only occurs when the ddr address range is set out of 32bit (4GB).
09-23-2020 04:05 PM
I am working for this recently, and meet the same question.
I have find out that vivado recent versions have a microblaze for 64 bit. It can have address of 64 bit.
But I meet another problem of UART in 64 microblaze can not printf question. I am work for this now.
Hope this can help you.
09-23-2020 06:21 PM
I just tested the DDR4 MIG and DMA using PL Logic example. The DDR and DMA works correct in the full range (8GB AXI Address) when I access the DMA axi-lite DRP interface using PL logic. I think the Microblaze DMA driver provided using in Xilinx DMA example has some problem to access the AXI address out of 4GB range.
09-26-2020 06:23 PM
The 64bit Microblaze processor works when I set the DDR4 address between 0x00000000~0xffffffff. If the DDR4 and DMA address set in address editor exceeds 4GB (for example 0x1_00000000~1_ffffffff), the processor enters exception and stalls after launching .elf program. I think the issue is caused by processor since the DDR MIG works correct when I access DMA and DRAM using PL logic directly.