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Anonymous
Not applicable
7,480 Views

Connecting 2 DDR3 memories to a single controller

Hi

 

 

I need to connect 2 DDR3 components (MT41K128M16JT) to a single memory controller.

I need that all the address/data lines will be connected to the memories together, except CS that will be separated (2 CS outputs from the FPGA ,one for each memory)

 

 

I'm using ARTIX-7 device, VIVADO 2013.1.

 

how can I configure the MIG to generate such controller.

Thanks

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-16-2007

Just select the target device in the MIG GUI and increase the data width to 32-bits which will use 2 of the x16 DDR3 components to make the 32-bits.

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Visitor
Visitor
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Registered: ‎11-06-2013

Once I select x32 as the data width, how do I connect the FPGA to the pair of DDR3 parts?  They will share address and control (fly by?) but the data bus will be x32.  How do I handle the clocks to each DDR3 part?  Fan out to both parts? 

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Visitor
Visitor
6,997 Views
Registered: ‎11-06-2013

I believe I will have to implement a fly-by topology for the clocks/control/address. AR 34557 & AR 35094 seem to address those issues. Along with UG 586, I think I'm okay.

I was assuming that if I picked a x16 DDR3 component and indicated to the MIG that I wanted x32 data bus that it would generate two ck outputs for the clock, at least.

I am using ISE 14.5, MIG v1.9, for xck410t.
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