06-11-2013 10:33 PM
I need to connect 2 DDR3 components (MT41K128M16JT) to a single memory controller.
I need that all the address/data lines will be connected to the memories together, except CS that will be separated (2 CS outputs from the FPGA ,one for each memory)
I'm using ARTIX-7 device, VIVADO 2013.1.
how can I configure the MIG to generate such controller.
06-13-2013 09:42 PM
Just select the target device in the MIG GUI and increase the data width to 32-bits which will use 2 of the x16 DDR3 components to make the 32-bits.
03-18-2014 08:55 AM
Once I select x32 as the data width, how do I connect the FPGA to the pair of DDR3 parts? They will share address and control (fly by?) but the data bus will be x32. How do I handle the clocks to each DDR3 part? Fan out to both parts?
03-18-2014 11:20 AM