UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Observer braydencdv
Observer
1,143 Views
Registered: ‎06-13-2018

Connecting a custom IP core to the DDR4 MIG

Jump to solution

HI,

 

I am trying to connect a custom IP block that is currently just a pass through from the MicroBlaze to the DDR4 SDRAMM MIG controller but am getting this error:

 

[BD 41-703] Peripheral </ddr4_0/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK> is mapped into master segment </microblaze_0/Data/SEG_ddr4_0_C0_DDR4_ADDRESS_BLOCK>, but there is no path between them. This is usually because an interconnect between the master and the peripheral has become misconfigured. Check and reconfigure the interconnect, or delete the master segment.

 

Any ideas on how to get around the error? Within the custom IP I am simply mapping the slave side signals from the microblaze to the master slave connected to the DDR4. 

 

Thanks

0 Kudos
1 Solution

Accepted Solutions
Observer braydencdv
Observer
1,189 Views
Registered: ‎06-13-2018

Re: Connecting a custom IP core to the DDR4 MIG

Jump to solution

To close the topic the errors above were in reference to the address editor. All that the error wanted was to unmap the unused  busses within the address editor. In the below image under the microblaze core the DDR4 under both Data and Instruction were the to slaves that needed to be unmapped. 

View solution in original post

4 Replies
Community Manager
Community Manager
1,091 Views
Registered: ‎07-23-2012

Re: Connecting a custom IP core to the DDR4 MIG

Jump to solution
Did you define the register space in the custom IP? To me it looks like the Microblaze is unable to find any registers connected to it and hence you see this issue.
-----------------------------------------------------------------------------------------------
Please mark the post as "Accept as solution" if the information provided answers your query/resolves your issue.

Give Kudos to a post which you think is helpful.
0 Kudos
Observer braydencdv
Observer
1,074 Views
Registered: ‎06-13-2018

Re: Connecting a custom IP core to the DDR4 MIG

Jump to solution

Are you referring to the below? If so then it is defined. If not can you specify what your referring to.

Address_editer.PNG

 

However one thing I forgot to add is that within the IP packager I have this warning message:  [IP_Flow 19-3153] Bus Interface 's00_axi_aclk': ASSOCIATED_BUSIF bus parameter is missing. I have one for the slave clock and master clock but from what the info I found they were able to just be ignored. 

 

Another thing is in the original error is one of 2 one that lists Data in the middle and another that lists Instruction in the middle. 

0 Kudos
Observer braydencdv
Observer
1,049 Views
Registered: ‎06-13-2018

Re: Connecting a custom IP core to the DDR4 MIG

Jump to solution

@smarell any other ideas on the topic? I have been stuck on this for days.

0 Kudos
Observer braydencdv
Observer
1,190 Views
Registered: ‎06-13-2018

Re: Connecting a custom IP core to the DDR4 MIG

Jump to solution

To close the topic the errors above were in reference to the address editor. All that the error wanted was to unmap the unused  busses within the address editor. In the below image under the microblaze core the DDR4 under both Data and Instruction were the to slaves that needed to be unmapped. 

View solution in original post