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frank_ma
Observer
Observer
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Registered: ‎09-10-2019

Constraint of SelectIO Speed

Hi Xilinx,

I found in UG571 that the SelectIO of Ultrascale+ can run up to 1600Mbps;

But the MIG can achieve DDR4-2667Mbps with the same HPIO.

So what is the main constraint if I want to run the SelectIO to a higher speed?

IOB/IOSerdes or the internal placement and routing? 

Thanks.

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joancab
Advisor
Advisor
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Registered: ‎05-11-2015

 

"run the SelectIO to a higher speed"

SelectIO is a number of different things and on top of that, configurable.

Also, higher speed than what?

 

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frank_ma
Observer
Observer
346 Views
Registered: ‎09-10-2019

Hi 

 

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joancab
Advisor
Advisor
317 Views
Registered: ‎05-11-2015

 

Check the AC and DC datasheet, for example for Kintex Ultrascale+ is DS922 (you don't mention which device you intend to use, only the architecture).

The maximum bit rate depends on things like the standard you need/ plan to use as well as the speed grade, among others. Look at tables 23 and 24 for LVDS, for example.

It looks like 1600 Mbps is the limit for interfaces other than MIG. Why? I don't know and probably you need someone very much into those things to tell you (if allowed to). 

If you look at those tables you will notice different speeds. You might also ask things like "why I can only reach 2133 Mb/s with a 2 rank DIMM DDR4 but 2400 Mb/s with 1 rank DIMM?" Well, they would have their reasons, there is one thing you can be sure of: they won't lie with that, if the device is capable of going faster they would immediately update the datasheet and advertise they got faster than before. So if they say "up to 1600", I would wake up of any dream of going faster.

For Gb speeds people use the MGT transceivers, not GPIOs

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