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Contributor
Contributor
1,062 Views
Registered: ‎02-17-2009

Controlling CS# pin of DDR3

Hi,

I am exploring MIG design on ARTY board as I have to use it in my project.

I have created two designs as below..

Design 1 --

.. Configured MIG tool with required options as per ARTY board except for CS# pin, which I have disabled.

.. Generated example design

.. There is no ddr3_cs_n port for mig component (as expected)

.. Manually added ddr3_cs_n port in example_top.vhd and controlling the assigned value from a dip-switch

.. Taken care of IO assignment and generated bit file

.. So my design in HW passes the DDR3 test when dip-switch is at 0 and fails when it is at 1. This is what I expected

 

Design-2

.. Generated a required block design for testing SPI boot load

.. Here too, I reconfigured MIG block not to have CS# pin

.. Generated wrapper and manually added ddr3_cs_n port in design_1_wrapper.vhd and controlling the assigned value from a dip-switch

.. Taken care of IO assignment and generated bit file

.. Exported to SDK and generated all required SWs (spi boot load & hello_world)

.. Now, after booting from SPI flash, design executes the code from DDR3 independent of dip-switch position.

.. I expected that, SW to fail execution from DDR3 when dip-sw is at 1, as ddr3_cs will be also 1.

.. So any guess ??

 

This is crucial, as I want my DDR3 to be in one bank of FPGA in my application, where I am using FTG256 device package.

If I remove, CS# pin from MIG then only it is possible. Otherwise it is taking two banks.

 

Regards

Prashant U

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2 Replies
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Contributor
Contributor
1,009 Views
Registered: ‎02-17-2009

Hi,

Well surprisingly no one has replied to my query.

Does any one has made it possible to interface artix-7 device in FTG256 package with DDR3 SDRAM (128Mb x 16) through single FPGA bank??

 

 

Regards

Prashant U

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Xilinx Employee
Xilinx Employee
1,006 Views
Registered: ‎09-20-2012

Hi @prashant_unch

 

The CKE and ODT can be placed on byte less pins, try doing this to fit x16 DDR3 with CS enabled in single IO bank.

 

CKE and ODT (or any other address/control pin) can be placed on the two pins in a bank that are not within one of the T0, T1, T2, or T3 byte groups (this includes the VRN/VRP pin locations for HP banks and the top or bottom pins of fully bonded HR banks) if ALL of the following conditions are met:

  • The pins are not used for some other function (for example, VRN/VRP pins of an HP bank are not being used for the DCI reference because either DCI cascade or external terminations are implemented).
  • AND the adjacent byte group (T0 or T3) is used as an address/control byte group.
  • AND one of the pins in that adjacent T0 or T3 byte group is either unused, a CK memory clock output, or an external VREF connection.

 

Thanks,
Deepika.
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