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voco-mannheim
Adventurer
Adventurer
9,298 Views
Registered: ‎10-16-2013

Critical warnigns in a MIG DDR3 implementation in Vivado 2014.2

Hi,

 

i get the following critical errors when i implement a MIG DDR3-controller application for the VC707 (see also attached screenshots):

 

  • [Netlist 29-160] Cannot set property 'VCCAUX_IO', because the property does not exist for objects of type 'pin'. ["c:/Users/C.Fonger/svn/FPGA/IOS/Source/ios_v7_repository/calc_step_2/test_src/mem_c_test2/mem_c_test2.srcs/sources_1/ip/mem_c_test2/mem_c_test2/user_design/constraints/mem_c_test2.xdc":543]
  • [Netlist 29-160] Cannot set property 'SLEW', because the property does not exist for objects of type 'pin'. ["c:/Users/C.Fonger/svn/FPGA/IOS/Source/ios_v7_repository/calc_step_2/test_src/mem_c_test2/mem_c_test2.srcs/sources_1/ip/mem_c_test2/mem_c_test2/user_design/constraints/mem_c_test2.xdc":544]
  • [Netlist 29-160] Cannot set property 'IOSTANDARD', because the property does not exist for objects of type 'pin'.
    ...

 

It is noticable the it only affects signals with the "std_logic_vector(0 downto 0)" type. All other DDR3-signals (e.g. dq, dqs, dm) are fine. Is it possible that the Vivado 2014.2 software have problems with the "0 downto 0" type? Can i ignore these warnings?

 

The same configuration works fine in Vivado 2013.3!

 

 

Thank's!

 

 

ddr3_critical_errors.jpg
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6 Replies
siktap
Scholar
Scholar
9,297 Views
Registered: ‎06-14-2012

Hi,

There was a known issue with MIG 2.0.

 

This occurs when the System Clock and Reference Clock are selected to be differential or single ended in the MiG GUI yet in the IP Integrator block design, those pins on the MiG core are not connected to the ports.

For instance they may be connected to outputs from an MMCM. 

To resolve the issue, it is necessary to regenerate the MiG IP core with No Buffer selected for these pins.

 

Please check with this as well.

 

Regards

Sikta

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voco-mannheim
Adventurer
Adventurer
9,290 Views
Registered: ‎10-16-2013

Hi,

 

thank's for the fast reply.

 

However this is not the solution. My first implementation was:

 

System Clock: No buffer

Reference Clock: Use system clock

 

Now, when i change this to (see attached screenshot):

 

System Clock: No buffer

Reference Clock: No buffer

 

 

i get the same critical errors. Btw, the MIG version is 2.1 in Vivado 2014.2 (according the mig_b.prj).

 

Do you have any others suggestions?

 

 

Thank's!

 

 

 

 

 

ddr3_critical_errors.jpg
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vsrunga
Xilinx Employee
Xilinx Employee
9,274 Views
Registered: ‎07-11-2011

Hi,

 

Is this in MIG standalone design or MIG as one of the modules?

When you use No Buffer I think VCAUX_IO constarint in XDC is no longer valid.

Did you check Claude's commens in below discussion and it don't help?

http://forums.xilinx.com/t5/MIG-Memory-Interface-Generator/Netlist-29-160-critical-warnings-Non-existing-properties/td-p/440366

 

Regards,

Vanitha

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njuers
Newbie
Newbie
9,228 Views
Registered: ‎09-09-2014

Hi,

 

I am experiencing similar problems with the MIG controller in vivado 2014.2.

There seems to be a lot ideas for a solution on these forums.

Has anyone actually been able to solve this problem in 2014.2 ?

If so what did they do ?

 

I have attempted to set the sys_clk and ref_clk to 'No_Buffer', however in doing this I was unable to route the now single ended outputs to the predefined differential ports on the MiniITX development kit I am using. Not sure how to get around this.

 

Regards,

 

Nathan

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ptaddoni
Contributor
Contributor
8,605 Views
Registered: ‎03-07-2013

Hello

 

I am experiencing the same problem in Vivado 2014.4, is there a fix or a workaround?

 

Here is an example:

 

[Netlist 29-160] Cannot set property 'VCCAUX_IO', because the property does not exist for objects of type 'pin'. ["c:/d4pp_fpga_viv/d4pp.srcs/sources_1/ip/ddr3_ifc_core_rev1/ddr3_ifc_core_rev1/user_design/constraints/ddr3_ifc_core_rev1.xdc":624]

 

# PadFunction: IO_L3P_T0_DQS_39
set_property VCCAUX_IO HIGH [get_ports {c0_ddr3_dqs_p[0]}]

 

Paul

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ptaddoni
Contributor
Contributor
8,561 Views
Registered: ‎03-07-2013

Hello

 

The fix for this problem was to change the declaration of the DQS pins from output (per the ISE example design) to

inout (per the Vivado example design).

 

-Paul

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